sys/dev/drm/i915/intel_display.c

1112

val = I915_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

1395

I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);

sys/dev/drm/i915/intel_display.c

1396

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

1400

DPLL(pipe),

sys/dev/drm/i915/intel_display.c

1449

I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);

sys/dev/drm/i915/intel_display.c

1453

DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,

sys/dev/drm/i915/intel_display.c

1488

WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);

sys/dev/drm/i915/intel_display.c

1512

i915_reg_t reg = DPLL(crtc->pipe);

sys/dev/drm/i915/intel_display.c

1531

I915_WRITE(DPLL(!crtc->pipe),

sys/dev/drm/i915/intel_display.c

1532

I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);

sys/dev/drm/i915/intel_display.c

15498

dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |

sys/dev/drm/i915/intel_display.c

15521

I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);

sys/dev/drm/i915/intel_display.c

15522

I915_WRITE(DPLL(pipe), dpll);

sys/dev/drm/i915/intel_display.c

15525

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

15533

I915_WRITE(DPLL(pipe), dpll);

sys/dev/drm/i915/intel_display.c

15537

I915_WRITE(DPLL(pipe), dpll);

sys/dev/drm/i915/intel_display.c

15538

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

15566

I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);

sys/dev/drm/i915/intel_display.c

15567

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

1577

I915_WRITE(DPLL(PIPE_B),

sys/dev/drm/i915/intel_display.c

1578

I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);

sys/dev/drm/i915/intel_display.c

1579

I915_WRITE(DPLL(PIPE_A),

sys/dev/drm/i915/intel_display.c

1580

I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);

sys/dev/drm/i915/intel_display.c

1590

I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);

sys/dev/drm/i915/intel_display.c

1591

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

1606

I915_WRITE(DPLL(pipe), val);

sys/dev/drm/i915/intel_display.c

1607

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

1623

I915_WRITE(DPLL(pipe), val);

sys/dev/drm/i915/intel_display.c

1624

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

1646

dpll_reg = DPLL(0);

sys/dev/drm/i915/intel_display.c

1650

dpll_reg = DPLL(0);

sys/dev/drm/i915/intel_display.c

7044

I915_WRITE(DPLL(pipe),

sys/dev/drm/i915/intel_display.c

7145

I915_WRITE(DPLL(pipe),

sys/dev/drm/i915/intel_display.c

8028

tmp = I915_READ(DPLL(crtc->pipe));

sys/dev/drm/i915/intel_display.c

8038

pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));

sys/dev/drm/i915/intel_dp.c

740

pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;

sys/dev/drm/i915/intel_dvo.c

478

dpll[pipe] = I915_READ(DPLL(pipe));

sys/dev/drm/i915/intel_dvo.c

479

I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);

sys/dev/drm/i915/intel_dvo.c

486

I915_WRITE(DPLL(pipe), dpll[pipe]);

sys/dev/drm/i915/intel_runtime_pm.c

1004

I915_WRITE(DPLL(pipe), val);

sys/dev/drm/i915/intel_runtime_pm.c

1158

(I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)

sys/dev/drm/i915/intel_runtime_pm.c

3634

uint32_t status = I915_READ(DPLL(PIPE_A));

sys/dev/drm/i915/intel_runtime_pm.c

998

u32 val = I915_READ(DPLL(pipe));