sys/dev/drm/amd/amdgpu/dce_v10_0.c

1113

tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1120

tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1139

tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1146

tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

169

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

183

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

202

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

215

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

234

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

252

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.h

107

uint32_t DPG_WATERMARK_MASK_CONTROL;

sys/dev/drm/amd/display/dc/dce/dce_mem_input.h

177

SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_mem_input.h

178

SFB(blk, DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_mem_input.h

188

SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_mem_input.h

222

SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\

sys/dev/drm/amd/display/dc/dce/dce_mem_input.h

52

SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\

sys/dev/drm/radeon/cik.c

9366

wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/cik.c

9370

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/cik.c

9375

tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/cik.c

9378

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/cik.c

9383

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);