sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

101

DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

104

DMCU_SF(DMCU_CTRL, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

106

DMCU_SF(DMCU_STATUS, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

108

DMCU_SF(DMCU_STATUS, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

110

DMCU_SF(DMCU_RAM_ACCESS_CTRL, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

112

DMCU_SF(DMCU_RAM_ACCESS_CTRL, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

114

DMCU_SF(DMCU_RAM_ACCESS_CTRL, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

116

DMCU_SF(MASTER_COMM_CMD_REG, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

118

DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

119

DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

123

DMCU_SF(DCI_MEM_PWR_STATUS, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

128

DMCU_SF(DMU_MEM_PWR_CNTL, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

78

DMCU_SF(DMCU_CTRL, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

80

DMCU_SF(DMCU_STATUS, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

82

DMCU_SF(DMCU_STATUS, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

84

DMCU_SF(DMCU_RAM_ACCESS_CTRL, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

86

DMCU_SF(DMCU_RAM_ACCESS_CTRL, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

88

DMCU_SF(DMCU_RAM_ACCESS_CTRL, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

90

DMCU_SF(MASTER_COMM_CMD_REG, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

92

DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

93

DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

95

DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

97

DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \

sys/dev/drm/amd/display/dc/dce/dce_dmcu.h

99

DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \