DMA_BLOCK
} else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
} else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
case DMA_BLOCK:
case DMA_BLOCK:
pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF;
pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
#define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */
#define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */
#define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */
#define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */
#define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */
#define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */
#define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */
#define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */
#define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */
#define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */
#define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */
#define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */
#define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */
#define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */
#define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */
#define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */
#define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */
#define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */
#define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */