sys/dev/drm/radeon/ni.c

1143

WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);

sys/dev/drm/radeon/ni.c

1784

tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);

sys/dev/drm/radeon/ni.c

1867

tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

sys/dev/drm/radeon/ni.c

1869

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/ni.c

881

case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):

sys/dev/drm/radeon/ni_dma.c

107

reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/ni_dma.c

169

rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

sys/dev/drm/radeon/ni_dma.c

171

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);

sys/dev/drm/radeon/ni_dma.c

200

reg_offset = DMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/ni_dma.c

62

reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/ni_dma.c

86

reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/si.c

1309

case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):

sys/dev/drm/radeon/si.c

3269

WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);

sys/dev/drm/radeon/si.c

3793

tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);

sys/dev/drm/radeon/si.c

3876

tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

sys/dev/drm/radeon/si.c

3878

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/si.c

4041

tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);

sys/dev/drm/radeon/si.c

4043

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/si.c

5527

offset = DMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/si.c

5539

offset = DMA1_REGISTER_OFFSET;

sys/dev/drm/radeon/si.c

5946

tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

sys/dev/drm/radeon/si.c

5947

WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/si.c

6061

dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;

sys/dev/drm/radeon/si.c

6094

WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);