wrmsr
wrmsr ; \
wrmsr ; \
wrmsr ; \
void wrmsr(u_int msr, u_int64_t newval);
wrmsr(0x17B, (v64 & ~0xFFFFFFFFLL) | 0x00000010LL);
wrmsr(MSR_THERM_CONTROL, ctl_value);
wrmsr(INTEL_MSR_PERF_BIAS, hint);
wrmsr(MSR_AMDK7_FIDVID_CTL, \
wrmsr(MSR_HV_HYPERCALL, hc);
wrmsr(MSR_HV_HYPERCALL, (hc & MSR_HV_HYPERCALL_RSVD_MASK));
wrmsr(MSR_HV_GUEST_OS_ID, MSR_HV_GUESTID_DRAGONFLY);
wrmsr(MSR_HV_EOM, 0);
wrmsr(MSR_HV_STIMER0_COUNT, current);
wrmsr(MSR_HV_SIMP, val);
wrmsr(MSR_HV_SIEFP, val);
wrmsr(sint, val);
wrmsr(sint, val);
wrmsr(MSR_HV_SCONTROL, val);
wrmsr(MSR_HV_STIMER0_COUNT, 0);
wrmsr(MSR_HV_STIMER0_CONFIG,
wrmsr(MSR_HV_SCONTROL, (orig & MSR_HV_SCTRL_RSVD_MASK));
wrmsr(sint, orig | MSR_HV_SINT_MASKED);
wrmsr(sint, orig | MSR_HV_SINT_MASKED);
wrmsr(MSR_HV_SIMP, (orig & MSR_HV_SIMP_RSVD_MASK));
wrmsr(MSR_HV_SIEFP, (orig & MSR_HV_SIEFP_RSVD_MASK));
wrmsr(MSR_HV_REFERENCE_TSC, val);
wrmsr(MSR_HV_REFERENCE_TSC, val & MSR_HV_REFTSC_RSVD_MASK);
struct nvmm_x86_exit_wrmsr wrmsr;
if (exit->u.wrmsr.msr == MSR_EFER) {
if (__predict_false(exit->u.wrmsr.val & ~EFER_VALID)) {
if ((vmcb->state.efer ^ exit->u.wrmsr.val) &
vmcb->state.efer = exit->u.wrmsr.val | EFER_SVME;
if (exit->u.wrmsr.msr == MSR_TSC) {
cpudata->gtsc_offset = exit->u.wrmsr.val - rdtsc();
if (msr_ignore_list[i] != exit->u.wrmsr.msr)
exit->u.wrmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
exit->u.wrmsr.val = (rdx << 32) | (rax & 0xFFFFFFFF);
exit->u.wrmsr.npc = cpudata->vmcb->ctrl.nrip;
wrmsr(MSR_STAR, svm_global_hstate.star);
wrmsr(MSR_LSTAR, svm_global_hstate.lstar);
wrmsr(MSR_CSTAR, svm_global_hstate.cstar);
wrmsr(MSR_SFMASK, svm_global_hstate.sfmask);
wrmsr(MSR_FSBASE, cpudata->hstate.fsbase);
wrmsr(MSR_KERNELGSBASE, cpudata->hstate.kernelgsbase);
wrmsr(MSR_VM_CR, msr & ~VM_CR_SVMED);
wrmsr(MSR_VM_HSAVE_PA, 0);
wrmsr(MSR_EFER, msr);
wrmsr(MSR_VM_HSAVE_PA, hsave[os_curcpu_number()].pa);
if (exit->u.wrmsr.msr == MSR_TSC) {
cpudata->gtsc_offset = exit->u.wrmsr.val - rdtsc();
if (exit->u.wrmsr.msr == MSR_CR_PAT) {
val = exit->u.wrmsr.val;
if (exit->u.wrmsr.msr == MSR_IA32_MISC_ENABLE) {
if (msr_ignore_list[i] != exit->u.wrmsr.msr)
exit->u.wrmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
exit->u.wrmsr.val = (rdx << 32) | (rax & 0xFFFFFFFF);
exit->u.wrmsr.npc = rip + inslen;
wrmsr(MSR_STAR, vmx_global_hstate.star);
wrmsr(MSR_LSTAR, vmx_global_hstate.lstar);
wrmsr(MSR_CSTAR, vmx_global_hstate.cstar);
wrmsr(MSR_SFMASK, vmx_global_hstate.sfmask);
wrmsr(MSR_KERNELGSBASE, cpudata->hstate.kernelgsbase);
wrmsr(MSR_IA32_FEATURE_CONTROL, msr |
wrmsr(AMD1X_MSR_PSTATE_CTL, cval);
wrmsr(INTEL_MSR_MISC_ENABLE, misc_enable);
wrmsr(INTEL_MSR_PERF_CTL, ctl);
wrmsr(MSR_APICBASE,
wrmsr(MSR_TSC_DEADLINE, val);
wrmsr(MSR_TSC_DEADLINE, val);
wrmsr(MSR_TSC_DEADLINE, val);
wrmsr(0xc0010055, msr & ~0x18000000ULL);
#define LAPIC_MSR_WRITE(msr, val) wrmsr((msr), (val))
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE);
wrmsr(msr, msrv);
wrmsr(msr, msrv);
wrmsr(msr, msrv);
wrmsr(msr, msrv);
wrmsr(msr + 1, msrv);
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
wrmsr(MSR_MTRRdefType, mtrrdef);
wrmsr(AMD0F_MSR_FIDVID_CTL, \
wrmsr(0x110B, msreg);
wrmsr(0x1107, msreg);
wrmsr(0x1107, msreg);
wrmsr(0x1107, msreg);
wrmsr(0x1107, msreg);
wrmsr(MSR_AMD_DE_CFG, msr);
wrmsr(0xc001001f, msr);
wrmsr(0xc001102a, msr);
wrmsr(0xc0011020, msr);
wrmsr(MSR_EFER, msr);
wrmsr(MSR_TSC_AUX, cpu);
wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[1] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP));
wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[0] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP));
wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[1] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP));
wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[0] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP));
wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[1] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP));
wrmsr(MSR_SPEC_CTRL, pscpu->trampoline.tr_pcb_spec_ctrl[0] & (SPEC_CTRL_IBRS|SPEC_CTRL_STIBP));
wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
wrmsr(MSR_KGSBASE, 0);
wrmsr(MSR_FSBASE, 0); /* User value */
wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
wrmsr(MSR_EFER, msr);
wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
wrmsr(MSR_STAR, msr);
wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL|PSL_AC);
wrmsr(MSR_FSBASE, 0); /* User value */
wrmsr(MSR_GSBASE, (u_int64_t)ps);
wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
wrmsr(MSR_EFER, msr);
wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
wrmsr(MSR_STAR, msr);
wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL|PSL_AC);
wrmsr(MSR_PAT, pat_msr);
wrmsr(MSR_FSBASE, gd->gd_user_fs);
wrmsr(MSR_KGSBASE, gd->gd_user_gs);
wrmsr(MSR_SPEC_CTRL,