sys/dev/drm/amd/amdgpu/gmc_v7_0.c

966

if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1084

if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

893

if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

190

SR(D1VGA_CONTROL), \

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

261

uint32_t D1VGA_CONTROL;

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

413

HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

1829

set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE);

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

1830

set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT);

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

1832

value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT);

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

1833

set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

433

set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

434

set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

436

value, 0, D1VGA_CONTROL, D1VGA_SYNC_POLARITY_SELECT);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

437

set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

393

REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

402

REG_WRITE(D1VGA_CONTROL, 0);