vm_fault
struct amdgpu_irq_src vm_fault;
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
adev->gmc.vm_fault.num_types = 1;
adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
adev->gmc.vm_fault.num_types = 1;
adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
adev->gmc.vm_fault.num_types = 1;
adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
&adev->gmc.vm_fault);
&adev->gmc.vm_fault);
int (*fault)(struct vm_area_struct *vma, struct vm_fault *vmf);
static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf)
static int ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
struct vm_fault *vmf)
struct vm_fault vmfs;
struct vm_fault *vmf = &vmfs;
return vm_fault(&vm->vm_map, trunc_page(va), prot, fault_flags);
rv = vm_fault(map, va, ftype, fault_flags);
rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
rv = vm_fault(map, va, ftype, fault_flags);
rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
int vm_fault(struct vm_map *, vm_offset_t, vm_prot_t, int);
rv = vm_fault(map, va, wire_prot, fault_flags);