sys/dev/drm/i915/i915_drv.h

3533

u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);

sys/dev/drm/i915/i915_sysfs.c

269

freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

sys/dev/drm/i915/intel_cdclk.c

471

val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);

sys/dev/drm/i915/intel_cdclk.c

545

val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);

sys/dev/drm/i915/intel_cdclk.c

549

if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &

sys/dev/drm/i915/intel_cdclk.c

625

val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);

sys/dev/drm/i915/intel_cdclk.c

629

if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &

sys/dev/drm/i915/intel_pm.c

314

val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);

sys/dev/drm/i915/intel_pm.c

323

if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &

sys/dev/drm/i915/intel_pm.c

336

val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);

sys/dev/drm/i915/intel_pm.c

5931

val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);

sys/dev/drm/i915/intel_pm.c

5944

val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);

sys/dev/drm/i915/intel_pm.c

5948

if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &

sys/dev/drm/i915/intel_pm.c

5954

val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);

sys/dev/drm/i915/intel_pm.c

7267

val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);

sys/dev/drm/i915/intel_pm.c

7295

val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);

sys/dev/drm/i915/intel_pm.c

7305

val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);

sys/dev/drm/i915/intel_pm.c

7315

val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);

sys/dev/drm/i915/intel_pm.c

7362

val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;

sys/dev/drm/i915/intel_pm.c

7487

val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

sys/dev/drm/i915/intel_pm.c

7660

val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

sys/dev/drm/i915/intel_pm.c

7744

val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

sys/dev/drm/i915/intel_runtime_pm.c

1440

state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);

sys/dev/drm/i915/intel_runtime_pm.c

1452

ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);

sys/dev/drm/i915/intel_runtime_pm.c

1473

((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)

sys/dev/drm/i915/intel_runtime_pm.c

1478

ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);

sys/dev/drm/i915/intel_runtime_pm.c

1486

vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));

sys/dev/drm/i915/intel_runtime_pm.c

888

((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)

sys/dev/drm/i915/intel_runtime_pm.c

893

ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);

sys/dev/drm/i915/intel_runtime_pm.c

901

vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));

sys/dev/drm/i915/intel_runtime_pm.c

935

state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;

sys/dev/drm/i915/intel_runtime_pm.c

949

ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;