sys/dev/drm/i915/i915_drv.h

3538

u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);

sys/dev/drm/i915/intel_cdclk.c

565

val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);

sys/dev/drm/i915/intel_cdclk.c

570

if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &

sys/dev/drm/i915/intel_display.c

1126

val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);

sys/dev/drm/i915/intel_display.c

186

hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &

sys/dev/drm/i915/intel_display.c

200

val = vlv_cck_read(dev_priv, reg);

sys/dev/drm/i915/intel_pm.c

7534

val = vlv_cck_read(dev_priv, CCK_FUSE_REG);

sys/dev/drm/i915/vlv_dsi_pll.c

166

if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &

sys/dev/drm/i915/vlv_dsi_pll.c

187

tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);

sys/dev/drm/i915/vlv_dsi_pll.c

278

pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);

sys/dev/drm/i915/vlv_dsi_pll.c

279

pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);