urtwn_read_4
if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
reg = urtwn_read_4(sc, R92C_SYS_CFG);
if (MS(urtwn_read_4(sc, R92C_HPON_FSM),
static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t);
reg = urtwn_read_4(sc, R92C_RCR);
if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00;
if (urtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
reg = urtwn_read_4(sc, R92C_MCUFWDL);
#define urtwn_bb_read urtwn_read_4
if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
reg = urtwn_read_4(sc, R92C_MCUFWDL);
if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
reg = urtwn_read_4(sc, R92C_RCR);
rcr = urtwn_read_4(sc, R92C_RCR);
reg = urtwn_read_4(sc, R92C_RRSR);
reg = urtwn_read_4(sc, R92C_TDECTRL);