sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

534

high = upper_32_bits(queue_address >> 8);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1037

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1040

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1048

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1051

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

475

upper_32_bits(guessed_wptr));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

479

upper_32_bits((uintptr_t)wptr));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

579

upper_32_bits(data64));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

646

high = upper_32_bits(queue_address >> 8);

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

157

cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

213

cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

217

cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

829

upper_32_bits(start));

sys/dev/drm/amd/amdgpu/amdgpu_vce.c

1040

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/amdgpu_vce.c

1058

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/amdgpu_vce.c

479

ib->ptr[ib->length_dw++] = upper_32_bits(dummy);

sys/dev/drm/amd/amdgpu/amdgpu_vce.c

657

amdgpu_set_ib_value(p, ib_idx, hi, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

251

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

258

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

317

upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

668

ib->ptr[ib->length_dw++] = upper_32_bits(dummy);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

720

ib->ptr[ib->length_dw++] = upper_32_bits(dummy);

sys/dev/drm/amd/amdgpu/atom.c

695

ctx->ctx->divmul[1] = upper_32_bits(val64);

sys/dev/drm/amd/amdgpu/atom.c

816

ctx->ctx->divmul[1] = upper_32_bits(val64);

sys/dev/drm/amd/amdgpu/cik_ih.c

136

WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1334

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1336

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1356

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/cik_sdma.c

231

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);

sys/dev/drm/amd/amdgpu/cik_sdma.c

279

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/cik_sdma.c

287

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/cik_sdma.c

288

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/drm/amd/amdgpu/cik_sdma.c

474

upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);

sys/dev/drm/amd/amdgpu/cik_sdma.c

638

amdgpu_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/drm/amd/amdgpu/cik_sdma.c

699

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/cik_sdma.c

754

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/drm/amd/amdgpu/cik_sdma.c

756

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/amd/amdgpu/cik_sdma.c

779

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/amd/amdgpu/cik_sdma.c

783

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/drm/amd/amdgpu/cik_sdma.c

807

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/amd/amdgpu/cik_sdma.c

809

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/drm/amd/amdgpu/cik_sdma.c

811

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/drm/amd/amdgpu/cik_sdma.c

858

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/drm/amd/amdgpu/cz_ih.c

138

WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2002

upper_32_bits(fb_location));

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2004

upper_32_bits(fb_location));

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2293

upper_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/drm/amd/amdgpu/dce_v10_0.c

245

upper_32_bits(crtc_base));

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2044

upper_32_bits(fb_location));

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2046

upper_32_bits(fb_location));

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2372

upper_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/drm/amd/amdgpu/dce_v11_0.c

263

upper_32_bits(crtc_base));

sys/dev/drm/amd/amdgpu/dce_v8_0.c

190

upper_32_bits(crtc_base));

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1914

upper_32_bits(fb_location));

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1916

upper_32_bits(fb_location));

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2194

upper_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2173

amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2176

amdgpu_ring_write(ring, upper_32_bits(seq - 1));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2185

amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2188

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2215

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2217

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2260

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2276

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2602

WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2612

WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2857

WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2923

mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2932

mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2959

mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2965

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3194

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3965

WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1680

ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1706

ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1732

ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4366

WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4370

WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4376

WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4450

amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4471

amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4473

amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4521

mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4525

mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4544

mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4554

mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4575

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4580

mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6161

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6177

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6195

amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6198

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6213

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6373

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6375

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6389

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6448

amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6481

amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7205

amdgpu_ring_write(ring, upper_32_bits(ce_payload_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7222

de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7227

de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7238

amdgpu_ring_write(ring, upper_32_bits(de_payload_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

905

ib.ptr[3] = upper_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1615

base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1623

base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1631

base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2693

WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2698

WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2702

WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2709

WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2779

upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2842

amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2866

amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2868

amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2899

upper_32_bits(ring->mqd_gpu_addr

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2904

mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2941

mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2951

mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2972

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2977

mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4043

WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4103

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4120

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4152

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4154

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4165

lower_32_bits(addr), upper_32_bits(addr),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4324

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4359

amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4372

de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4381

amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4430

amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4462

amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

462

ib.ptr[3] = upper_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

241

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

46

upper_32_bits(value));

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

441

upper_32_bits(pd_addr));

sys/dev/drm/amd/amdgpu/iceland_ih.c

138

WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

260

upper_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

63

upper_32_bits(value));

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

110

upper_32_bits(adev->doorbell.base));

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

105

upper_32_bits(adev->doorbell.base));

sys/dev/drm/amd/amdgpu/psp_v10_0.c

169

cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

217

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

314

write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

316

write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

237

cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

285

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

379

write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

381

write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

287

cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

335

psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

434

write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

436

write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1218

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1220

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1240

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

258

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

309

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

317

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

318

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

450

upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

572

amdgpu_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

633

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

692

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

694

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

717

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

721

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

745

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

747

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

749

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

796

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1016

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1018

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1020

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1067

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1657

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1659

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1679

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

432

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

483

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

491

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

492

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

689

upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

715

upper_32_bits(wptr_gpu_addr));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

844

amdgpu_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

905

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

963

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

965

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

988

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

992

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1016

amdgpu_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1077

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1136

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1138

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1163

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1167

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1192

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1194

ib->ptr[ib->length_dw++] = upper_32_bits(flags);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1196

ib->ptr[ib->length_dw++] = upper_32_bits(addr);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1241

upper_32_bits(addr) & 0xffffffff,

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1781

ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1783

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1803

ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

407

upper_32_bits(ring->wptr << 2));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

420

upper_32_bits(ring->wptr << 2));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

422

WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

458

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

533

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

543

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

544

amdgpu_ring_write(ring, upper_32_bits(seq));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

720

upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

736

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

777

upper_32_bits(wptr_gpu_addr));

sys/dev/drm/amd/amdgpu/tonga_ih.c

144

WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

357

WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

459

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

264

upper_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

409

WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

415

upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

475

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

544

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1016

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1035

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1073

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1101

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

236

ib->ptr[ib->length_dw++] = upper_32_bits(dummy);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

298

ib->ptr[ib->length_dw++] = upper_32_bits(dummy);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

596

upper_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

832

WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

838

upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

853

WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

860

WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

914

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

941

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1080

(upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1086

upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1102

WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1109

WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1175

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1207

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1317

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1337

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

244

ib->ptr[ib->length_dw++] = upper_32_bits(dummy);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

305

ib->ptr[ib->length_dw++] = upper_32_bits(dummy);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

683

upper_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

694

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

701

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

730

WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

816

upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

822

upper_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

833

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

840

upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

907

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

247

WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

254

WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

285

WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

292

WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

299

WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

846

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

869

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

164

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

236

upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

340

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

348

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

356

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI3), upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

960

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

971

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1078

(upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1084

upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1346

amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1385

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1510

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1534

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1678

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1702

amdgpu_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1749

amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1761

amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1888

val = upper_32_bits(ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

299

upper_32_bits(adev->vcn.gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

311

upper_32_bits(adev->vcn.gpu_addr + offset));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

319

upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

369

upper_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

381

upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

392

upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

905

(upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

911

upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

929

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

936

WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

944

WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vega10_ih.c

132

WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFFFF);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3545

plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3552

= upper_32_bits(afb->address);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3557

= upper_32_bits(chroma_addr);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4320

attributes.address.high_part = upper_32_bits(address);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4443

addr.address.grph.addr.high_part = upper_32_bits(afb->address);

sys/dev/drm/amd/powerplay/amd_powerplay.c

161

upper_32_bits((unsigned long)cpu_ptr),

sys/dev/drm/amd/powerplay/amd_powerplay.c

163

upper_32_bits(gpu_addr),

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

129

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

161

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

319

entry->image_addr_high = upper_32_bits(info.mc_addr);

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

358

upper_32_bits(smu_data->smu_buffer.mc_addr));

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

426

smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data->header_buffer.mc_addr));

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

215

reg_data = upper_32_bits(info.mc_addr) &

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

355

task->addr.high = upper_32_bits(smu8_smu->scratch_buffer[i].mc_addr);

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

392

task->addr.high = upper_32_bits(smu8_smu->driver_buffer[i].mc_addr);

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

620

upper_32_bits(smu8_smu->scratch_buffer[i].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

647

upper_32_bits(smu8_smu->scratch_buffer[i].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

681

upper_32_bits(smu8_smu->toc_buffer.mc_addr));

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

132

upper_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

49

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

80

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

190

upper_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr)))

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

54

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

96

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

179

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

222

upper_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

250

upper_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

275

upper_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

362

upper_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr));

sys/dev/drm/i915/i915_drv.c

523

upper_32_bits(rman_get_start(dev_priv->mch_res)));

sys/dev/drm/i915/i915_gem_execbuffer.c

1291

*batch++ = upper_32_bits(addr);

sys/dev/drm/i915/i915_gem_execbuffer.c

1298

*batch++ = upper_32_bits(addr);

sys/dev/drm/i915/i915_gem_execbuffer.c

1299

*batch++ = upper_32_bits(target_offset);

sys/dev/drm/i915/i915_gem_execbuffer.c

1303

*batch++ = upper_32_bits(addr);

sys/dev/drm/i915/i915_gem_execbuffer.c

1305

*batch++ = upper_32_bits(target_offset);

sys/dev/drm/i915/i915_gem_fence_reg.c

110

I915_WRITE(fence_reg_hi, upper_32_bits(val));

sys/dev/drm/i915/i915_gem_gtt.c

1319

I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));

sys/dev/drm/i915/i915_gem_gtt.c

1328

I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));

sys/dev/drm/i915/i915_gem_gtt.c

2393

upper_32_bits(fault_addr),

sys/dev/drm/i915/i915_gem_gtt.c

3235

I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));

sys/dev/drm/i915/i915_gem_render_state.c

105

s = upper_32_bits(r);

sys/dev/drm/i915/i915_gpu_error.c

383

upper_32_bits(err->gtt_offset),

sys/dev/drm/i915/i915_gpu_error.c

494

upper_32_bits(start), lower_32_bits(start),

sys/dev/drm/i915/i915_gpu_error.c

495

upper_32_bits(end), lower_32_bits(end));

sys/dev/drm/i915/i915_gpu_error.c

504

err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),

sys/dev/drm/i915/i915_gpu_error.c

577

upper_32_bits(obj->gtt_offset),

sys/dev/drm/i915/i915_gpu_error.c

781

upper_32_bits(obj->gtt_offset),

sys/dev/drm/i915/i915_perf.c

1289

upper_32_bits(ce->lrc_desc);

sys/dev/drm/i915/i915_perf.c

1300

i915->perf.oa.specific_ctx_id = upper_32_bits(ce->lrc_desc);

sys/dev/drm/i915/i915_vma.c

625

if (upper_32_bits(end - 1) &&

sys/dev/drm/i915/i915_vma.h

206

GEM_BUG_ON(upper_32_bits(vma->node.start));

sys/dev/drm/i915/i915_vma.h

207

GEM_BUG_ON(upper_32_bits(vma->node.start + vma->node.size - 1));

sys/dev/drm/i915/intel_engine_cs.c

1321

upper_32_bits(addr), lower_32_bits(addr));

sys/dev/drm/i915/intel_engine_cs.c

1324

upper_32_bits(addr), lower_32_bits(addr));

sys/dev/drm/i915/intel_engine_cs.c

1333

upper_32_bits(addr), lower_32_bits(addr));

sys/dev/drm/i915/intel_engine_cs.c

1416

rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,

sys/dev/drm/i915/intel_guc_fw.c

170

I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);

sys/dev/drm/i915/intel_huc_fw.c

124

I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);

sys/dev/drm/i915/intel_lrc.c

2039

*cs++ = upper_32_bits(pd_daddr);

sys/dev/drm/i915/intel_lrc.c

2101

*cs++ = upper_32_bits(offset);

sys/dev/drm/i915/intel_lrc.c

2450

upper_32_bits(ce->lrc_desc);

sys/dev/drm/i915/intel_lrc.c

463

writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);

sys/dev/drm/i915/intel_lrc.c

465

writel(upper_32_bits(desc), execlists->submit_reg);

sys/dev/drm/i915/intel_lrc.c

504

GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));

sys/dev/drm/i915/intel_lrc.c

564

upper_32_bits(ce->lrc_desc));

sys/dev/drm/i915/intel_lrc_reg.h

52

(reg_state__)[CTX_PDP ## n ## _UDW + 1] = upper_32_bits(addr__); \

sys/dev/drm/i915/intel_lrc_reg.h

59

(reg_state__)[CTX_PDP0_UDW + 1] = upper_32_bits(addr__); \

sys/dev/drm/radeon/atombios_crtc.c

1384

upper_32_bits(fb_location));

sys/dev/drm/radeon/atombios_crtc.c

1386

upper_32_bits(fb_location));

sys/dev/drm/radeon/atombios_crtc.c

1585

WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));

sys/dev/drm/radeon/atombios_crtc.c

1586

WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));

sys/dev/drm/radeon/atombios_crtc.c

1588

WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));

sys/dev/drm/radeon/atombios_crtc.c

1589

WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));

sys/dev/drm/radeon/cik.c

3581

radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) |

sys/dev/drm/radeon/cik.c

3593

radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));

sys/dev/drm/radeon/cik.c

3621

radeon_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/radeon/cik.c

3647

radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);

sys/dev/drm/radeon/cik.c

3709

radeon_ring_write(ring, upper_32_bits(src_offset));

sys/dev/drm/radeon/cik.c

3711

radeon_ring_write(ring, upper_32_bits(dst_offset));

sys/dev/drm/radeon/cik.c

3770

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));

sys/dev/drm/radeon/cik.c

3781

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

sys/dev/drm/radeon/cik.c

4109

WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/cik.c

4122

WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/drm/radeon/cik.c

4567

WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);

sys/dev/drm/radeon/cik.c

4668

mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);

sys/dev/drm/radeon/cik.c

4679

mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);

sys/dev/drm/radeon/cik.c

4707

mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/drm/radeon/cik.c

4719

upper_32_bits(wb_gpu_addr) & 0xffff;

sys/dev/drm/radeon/cik.c

6645

WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));

sys/dev/drm/radeon/cik.c

7007

WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/cik_sdma.c

144

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));

sys/dev/drm/radeon/cik_sdma.c

154

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));

sys/dev/drm/radeon/cik_sdma.c

207

radeon_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/radeon/cik_sdma.c

236

radeon_ring_write(ring, upper_32_bits(addr));

sys/dev/drm/radeon/cik_sdma.c

399

upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);

sys/dev/drm/radeon/cik_sdma.c

613

radeon_ring_write(ring, upper_32_bits(src_offset));

sys/dev/drm/radeon/cik_sdma.c

615

radeon_ring_write(ring, upper_32_bits(dst_offset));

sys/dev/drm/radeon/cik_sdma.c

669

radeon_ring_write(ring, upper_32_bits(gpu_addr));

sys/dev/drm/radeon/cik_sdma.c

727

ib.ptr[2] = upper_32_bits(gpu_addr);

sys/dev/drm/radeon/cik_sdma.c

816

ib->ptr[ib->length_dw++] = upper_32_bits(src);

sys/dev/drm/radeon/cik_sdma.c

818

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/radeon/cik_sdma.c

857

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/radeon/cik_sdma.c

870

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/drm/radeon/cik_sdma.c

910

ib->ptr[ib->length_dw++] = upper_32_bits(pe);

sys/dev/drm/radeon/cik_sdma.c

914

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/drm/radeon/evergreen.c

1409

upper_32_bits(crtc_base));

sys/dev/drm/radeon/evergreen.c

2752

upper_32_bits(rdev->mc.vram_start));

sys/dev/drm/radeon/evergreen.c

2754

upper_32_bits(rdev->mc.vram_start));

sys/dev/drm/radeon/evergreen.c

2762

WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));

sys/dev/drm/radeon/evergreen.c

2931

radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));

sys/dev/drm/radeon/evergreen.c

2942

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);

sys/dev/drm/radeon/evergreen.c

3086

WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/evergreen.c

4269

dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));

sys/dev/drm/radeon/evergreen.c

4276

data = upper_32_bits(reg_list_mc_addr);

sys/dev/drm/radeon/evergreen_cs.c

1822

ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/drm/radeon/evergreen_cs.c

1868

ib[idx+1] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

1903

ib[idx+1] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

1931

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2024

ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2104

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2165

ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/drm/radeon/evergreen_cs.c

2203

ib[idx+3] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2251

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2273

ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/drm/radeon/evergreen_cs.c

2295

ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/drm/radeon/evergreen_cs.c

2425

(upper_32_bits(offset64) & 0xff);

sys/dev/drm/radeon/evergreen_cs.c

2505

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2524

ib[idx+4] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2553

ib[idx+1] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2578

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2605

ib[idx+4] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2654

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2839

ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2883

ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2884

ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2899

ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2905

ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2942

ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2943

ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2954

ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2956

ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2992

ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2993

ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

2994

ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

3032

ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

3048

ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

3052

ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

3094

ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

3110

ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

3116

ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

3181

ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/evergreen_cs.c

3203

ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;

sys/dev/drm/radeon/evergreen_dma.c

141

radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);

sys/dev/drm/radeon/evergreen_dma.c

142

radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);

sys/dev/drm/radeon/evergreen_dma.c

47

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));

sys/dev/drm/radeon/evergreen_dma.c

77

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);

sys/dev/drm/radeon/evergreen_dma.c

88

radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));

sys/dev/drm/radeon/ni.c

1430

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));

sys/dev/drm/radeon/ni.c

1460

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);

sys/dev/drm/radeon/ni.c

1714

WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);

sys/dev/drm/radeon/ni_dma.c

133

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);

sys/dev/drm/radeon/ni_dma.c

144

radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));

sys/dev/drm/radeon/ni_dma.c

221

upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);

sys/dev/drm/radeon/ni_dma.c

329

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/drm/radeon/ni_dma.c

330

ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;

sys/dev/drm/radeon/ni_dma.c

369

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/drm/radeon/ni_dma.c

381

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/drm/radeon/ni_dma.c

421

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/drm/radeon/ni_dma.c

425

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/drm/radeon/r100.c

3869

upper_32_bits(rdev->mc.agp_base) & 0xff);

sys/dev/drm/radeon/r300.c

100

((upper_32_bits(addr) & 0xff) << 24);

sys/dev/drm/radeon/r300.c

1338

upper_32_bits(rdev->mc.agp_base) & 0xff);

sys/dev/drm/radeon/r520.c

157

S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));

sys/dev/drm/radeon/r600.c

2759

WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/r600.c

2898

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));

sys/dev/drm/radeon/r600.c

2948

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);

sys/dev/drm/radeon/r600.c

3008

tmp = upper_32_bits(src_offset) & 0xff;

sys/dev/drm/radeon/r600.c

3015

radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);

sys/dev/drm/radeon/r600.c

3395

radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));

sys/dev/drm/radeon/r600.c

3406

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);

sys/dev/drm/radeon/r600.c

3733

WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/r600_cs.c

1678

ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/drm/radeon/r600_cs.c

1719

ib[idx+1] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

1771

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

1815

ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/drm/radeon/r600_cs.c

1845

ib[idx+3] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

1883

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

1905

ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);

sys/dev/drm/radeon/r600_cs.c

2012

(upper_32_bits(offset64) & 0xff);

sys/dev/drm/radeon/r600_cs.c

2154

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

2173

ib[idx+4] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

2202

ib[idx+1] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

2227

ib[idx+2] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

2251

ib[idx+4] = upper_32_bits(offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

2418

ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

2450

ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

2456

ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

2472

ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

2473

ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

2483

ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff;

sys/dev/drm/radeon/r600_cs.c

2484

ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16;

sys/dev/drm/radeon/r600_cs.c

2517

ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;

sys/dev/drm/radeon/r600_dma.c

142

upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/r600_dma.c

254

radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);

sys/dev/drm/radeon/r600_dma.c

294

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));

sys/dev/drm/radeon/r600_dma.c

321

radeon_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/drm/radeon/r600_dma.c

359

ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;

sys/dev/drm/radeon/r600_dma.c

414

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);

sys/dev/drm/radeon/r600_dma.c

425

radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));

sys/dev/drm/radeon/r600_dma.c

477

radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |

sys/dev/drm/radeon/r600_dma.c

478

(upper_32_bits(src_offset) & 0xff)));

sys/dev/drm/radeon/r600_dpm.c

526

WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask));

sys/dev/drm/radeon/radeon_cursor.c

109

upper_32_bits(radeon_crtc->cursor_addr));

sys/dev/drm/radeon/radeon_cursor.c

112

upper_32_bits(radeon_crtc->cursor_addr));

sys/dev/drm/radeon/radeon_cursor.c

98

upper_32_bits(radeon_crtc->cursor_addr));

sys/dev/drm/radeon/radeon_vce.c

383

ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));

sys/dev/drm/radeon/radeon_vce.c

437

ib.ptr[ib.length_dw++] = cpu_to_le32(upper_32_bits(dummy));

sys/dev/drm/radeon/radeon_vce.c

724

radeon_ring_write(ring, cpu_to_le32(upper_32_bits(ib->gpu_addr)));

sys/dev/drm/radeon/radeon_vce.c

743

radeon_ring_write(ring, cpu_to_le32(upper_32_bits(addr)));

sys/dev/drm/radeon/rs400.c

160

tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;

sys/dev/drm/radeon/rs400.c

218

((upper_32_bits(addr) & 0xff) << 4);

sys/dev/drm/radeon/rv515.c

384

upper_32_bits(rdev->mc.vram_start));

sys/dev/drm/radeon/rv515.c

386

upper_32_bits(rdev->mc.vram_start));

sys/dev/drm/radeon/rv515.c

389

upper_32_bits(rdev->mc.vram_start));

sys/dev/drm/radeon/rv515.c

391

upper_32_bits(rdev->mc.vram_start));

sys/dev/drm/radeon/rv515.c

488

S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));

sys/dev/drm/radeon/rv770.c

815

WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));

sys/dev/drm/radeon/rv770.c

816

WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));

sys/dev/drm/radeon/rv770.c

818

WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));

sys/dev/drm/radeon/rv770.c

819

WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));

sys/dev/drm/radeon/rv770_dma.c

77

radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);

sys/dev/drm/radeon/rv770_dma.c

78

radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);

sys/dev/drm/radeon/si.c

3382

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));

sys/dev/drm/radeon/si.c

3415

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));

sys/dev/drm/radeon/si.c

3428

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

sys/dev/drm/radeon/si.c

3669

WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/si.c

3700

WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/si.c

3724

WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/si.c

6009

WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/si_dma.c

122

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/drm/radeon/si_dma.c

134

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/drm/radeon/si_dma.c

174

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/drm/radeon/si_dma.c

178

ib->ptr[ib->length_dw++] = upper_32_bits(value);

sys/dev/drm/radeon/si_dma.c

266

radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);

sys/dev/drm/radeon/si_dma.c

267

radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);

sys/dev/drm/radeon/si_dma.c

83

ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;

sys/dev/drm/radeon/si_dma.c

84

ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;

sys/dev/drm/radeon/uvd_v1_0.c

364

WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |

sys/dev/drm/radeon/uvd_v2_2.c

50

radeon_ring_write(ring, upper_32_bits(addr) & 0xff);

sys/dev/drm/radeon/vce_v1_0.c

302

WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/radeon/vce_v1_0.c

309

WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/netif/oce/oce_mbox.c

1170

sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr));

sys/dev/netif/oce/oce_mbox.c

1206

sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr));

sys/dev/netif/oce/oce_mbox.c

1444

sgl->pa_hi = upper_32_bits(pdma_mem->paddr);

sys/dev/netif/oce/oce_mbox.c

1588

fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr);

sys/dev/netif/oce/oce_mbox.c

1874

sgl->pa_hi = htole32(upper_32_bits(dma.paddr));

sys/dev/netif/oce/oce_mbox.c

1996

sgl->pa_hi = htole32(upper_32_bits(dma.paddr));

sys/dev/netif/oce/oce_mbox.c

2088

sgl->pa_hi = htole32(upper_32_bits(dma.paddr));