sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

107

enum bw_defines tiling_mode[maximum_number_of_surfaces];

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1095

if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] != bw_def_linear) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

1098

else if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] == bw_def_linear && bw_equ(bw_mod((bw_mul(data->pitch_in_pixels_after_surface_type[i], bw_int_to_fixed(data->bytes_per_pixel[i]))), data->inefficient_linear_pitch_in_bytes), bw_int_to_fixed(0))) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

258

tiling_mode[0] = bw_def_linear;

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

259

tiling_mode[1] = bw_def_linear;

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

260

tiling_mode[2] = bw_def_linear;

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

261

tiling_mode[3] = bw_def_linear;

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

264

tiling_mode[0] = bw_def_landscape;

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

265

tiling_mode[1] = bw_def_landscape;

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

266

tiling_mode[2] = bw_def_landscape;

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

267

tiling_mode[3] = bw_def_landscape;

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

323

tiling_mode[i] = bw_def_linear;

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

326

tiling_mode[i] = bw_def_tiled;

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

370

tiling_mode[maximum_number_of_surfaces - 2] = bw_def_linear;

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

371

tiling_mode[maximum_number_of_surfaces - 1] = bw_def_linear;

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

578

if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && (tiling_mode[i] == bw_def_linear || data->stereo_mode[i] != bw_def_mono)) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

677

else if (tiling_mode[i] == bw_def_linear) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

862

if ((dceip->dmif_pipe_en_fbc_chunk_tracker + 3 == i && fbc_enabled == 0 && tiling_mode[i] != bw_def_linear)) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

991

if (tiling_mode[i] == bw_def_linear) {

sys/dev/drm/i915/i915_gem_tiling.c

178

int tiling_mode, unsigned int stride)

sys/dev/drm/i915/i915_gem_tiling.c

186

size = i915_gem_fence_size(i915, vma->size, tiling_mode, stride);

sys/dev/drm/i915/i915_gem_tiling.c

190

alignment = i915_gem_fence_alignment(i915, vma->size, tiling_mode, stride);

sys/dev/drm/i915/i915_gem_tiling.c

200

int tiling_mode, unsigned int stride)

sys/dev/drm/i915/i915_gem_tiling.c

205

if (tiling_mode == I915_TILING_NONE)

sys/dev/drm/i915/i915_gem_tiling.c

209

if (i915_vma_fence_prepare(vma, tiling_mode, stride))

sys/dev/drm/i915/i915_gem_tiling.c

351

if (!i915_tiling_ok(obj, args->tiling_mode, args->stride)) {

sys/dev/drm/i915/i915_gem_tiling.c

356

if (args->tiling_mode == I915_TILING_NONE) {

sys/dev/drm/i915/i915_gem_tiling.c

360

if (args->tiling_mode == I915_TILING_X)

sys/dev/drm/i915/i915_gem_tiling.c

379

args->tiling_mode = I915_TILING_NONE;

sys/dev/drm/i915/i915_gem_tiling.c

389

err = i915_gem_object_set_tiling(obj, args->tiling_mode, args->stride);

sys/dev/drm/i915/i915_gem_tiling.c

394

args->tiling_mode = i915_gem_object_get_tiling(obj);

sys/dev/drm/i915/i915_gem_tiling.c

426

args->tiling_mode =

sys/dev/drm/i915/i915_gem_tiling.c

434

switch (args->tiling_mode) {

sys/dev/drm/include/uapi/drm/i915_drm.h

1223

__u32 tiling_mode;

sys/dev/drm/include/uapi/drm/i915_drm.h

1246

__u32 tiling_mode;