sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

42

dpp->tf_regs->reg

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

546

const struct dcn_dpp_registers *tf_regs,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

556

dpp->tf_regs = tf_regs;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h

1347

const struct dcn_dpp_registers *tf_regs;

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.h

1507

const struct dcn_dpp_registers *tf_regs,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

43

dpp->tf_regs->reg

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

43

dpp->tf_regs->reg

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

384

static const struct dcn_dpp_registers tf_regs[] = {

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

385

tf_regs(0),

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

386

tf_regs(1),

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

387

tf_regs(2),

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

388

tf_regs(3),

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

577

&tf_regs[inst], &tf_shift, &tf_mask);