sys/dev/drm/i915/i915_reg.h

10751

#define TC_LIVE_STATE_TBT(tc_port) (1 << ((tc_port) * 8 + 6))

sys/dev/drm/i915/i915_reg.h

10752

#define TC_LIVE_STATE_TC(tc_port) (1 << ((tc_port) * 8 + 5))

sys/dev/drm/i915/i915_reg.h

10753

#define DP_LANE_ASSIGNMENT_SHIFT(tc_port) ((tc_port) * 8)

sys/dev/drm/i915/i915_reg.h

10754

#define DP_LANE_ASSIGNMENT_MASK(tc_port) (0xf << ((tc_port) * 8))

sys/dev/drm/i915/i915_reg.h

10755

#define DP_LANE_ASSIGNMENT(tc_port, x) ((x) << ((tc_port) * 8))

sys/dev/drm/i915/i915_reg.h

10758

#define DP_PHY_MODE_STATUS_COMPLETED(tc_port) (1 << (tc_port))

sys/dev/drm/i915/i915_reg.h

10761

#define DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))

sys/dev/drm/i915/i915_reg.h

2038

#define MG_MISC_SUS0(tc_port) \

sys/dev/drm/i915/i915_reg.h

2039

_MMIO(_PORT(tc_port, MG_MISC_SUS0_PORT1, MG_MISC_SUS0_PORT2))

sys/dev/drm/i915/i915_reg.h

2098

#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))

sys/dev/drm/i915/i915_reg.h

2099

#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))

sys/dev/drm/i915/i915_reg.h

2100

#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))

sys/dev/drm/i915/i915_reg.h

2101

#define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))

sys/dev/drm/i915/i915_reg.h

2102

#define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))

sys/dev/drm/i915/i915_reg.h

2103

#define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port)))

sys/dev/drm/i915/i915_reg.h

7204

#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16))

sys/dev/drm/i915/i915_reg.h

7213

#define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port))

sys/dev/drm/i915/i915_reg.h

7221

#define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4)

sys/dev/drm/i915/i915_reg.h

7222

#define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4)

sys/dev/drm/i915/i915_reg.h

7223

#define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)

sys/dev/drm/i915/i915_reg.h

7224

#define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4)

sys/dev/drm/i915/i915_reg.h

7588

#define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24))

sys/dev/drm/i915/i915_reg.h

7677

#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4)

sys/dev/drm/i915/i915_reg.h

7782

#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)

sys/dev/drm/i915/i915_reg.h

7783

#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)

sys/dev/drm/i915/i915_reg.h

9347

#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \

sys/dev/drm/i915/i915_reg.h

9348

21 : (tc_port) + 12))

sys/dev/drm/i915/intel_ddi.c

2743

enum tc_port tc_port = intel_port_to_tc(dev_priv, port);

sys/dev/drm/i915/intel_ddi.c

2745

return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);

sys/dev/drm/i915/intel_display.c

6023

enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)

sys/dev/drm/i915/intel_dp.c

177

enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);

sys/dev/drm/i915/intel_dp.c

180

if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)

sys/dev/drm/i915/intel_dp.c

184

DP_LANE_ASSIGNMENT_MASK(tc_port)) >>

sys/dev/drm/i915/intel_dp.c

185

DP_LANE_ASSIGNMENT_SHIFT(tc_port);

sys/dev/drm/i915/intel_dp.c

231

enum tc_port tc_port = intel_port_to_tc(dev_priv, port);

sys/dev/drm/i915/intel_dp.c

234

if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)

sys/dev/drm/i915/intel_dp.c

246

DP_LANE_ASSIGNMENT_MASK(tc_port)) >>

sys/dev/drm/i915/intel_dp.c

247

DP_LANE_ASSIGNMENT_SHIFT(tc_port);

sys/dev/drm/i915/intel_dp.c

296

enum tc_port tc_port = intel_port_to_tc(dev_priv, port);

sys/dev/drm/i915/intel_dp.c

301

if (tc_port == PORT_TC_NONE)

sys/dev/drm/i915/intel_dp.c

314

val = I915_READ(MG_MISC_SUS0(tc_port));

sys/dev/drm/i915/intel_dp.c

322

I915_WRITE(MG_MISC_SUS0(tc_port), val);

sys/dev/drm/i915/intel_dp.c

329

enum tc_port tc_port = intel_port_to_tc(dev_priv, port);

sys/dev/drm/i915/intel_dp.c

334

if (tc_port == PORT_TC_NONE)

sys/dev/drm/i915/intel_dp.c

347

val = I915_READ(MG_MISC_SUS0(tc_port));

sys/dev/drm/i915/intel_dp.c

355

I915_WRITE(MG_MISC_SUS0(tc_port), val);

sys/dev/drm/i915/intel_dp.c

4841

enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);

sys/dev/drm/i915/intel_dp.c

4849

if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {

sys/dev/drm/i915/intel_dp.c

4850

DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);

sys/dev/drm/i915/intel_dp.c

4859

if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {

sys/dev/drm/i915/intel_dp.c

4860

val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);

sys/dev/drm/i915/intel_dp.c

4869

!(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {

sys/dev/drm/i915/intel_dp.c

4870

DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);

sys/dev/drm/i915/intel_dp.c

4872

val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);

sys/dev/drm/i915/intel_dp.c

4887

enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);

sys/dev/drm/i915/intel_dp.c

4899

if (val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)) {

sys/dev/drm/i915/intel_dp.c

4900

val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);

sys/dev/drm/i915/intel_dp.c

4919

enum tc_port tc_port = intel_port_to_tc(dev_priv, port);

sys/dev/drm/i915/intel_dp.c

4923

is_legacy = I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port);

sys/dev/drm/i915/intel_dp.c

4930

is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);

sys/dev/drm/i915/intel_dp.c

4931

is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);

sys/dev/drm/i915/intel_drv.h

1537

enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,