sys/dev/drm/amd/amdgpu/si_dpm.c

1842

static int si_write_smc_soft_register(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/si_dpm.c

2822

ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);

sys/dev/drm/amd/amdgpu/si_dpm.c

3827

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);

sys/dev/drm/amd/amdgpu/si_dpm.c

4105

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);

sys/dev/drm/amd/amdgpu/si_dpm.c

4122

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);

sys/dev/drm/amd/amdgpu/si_dpm.c

4123

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);

sys/dev/drm/amd/amdgpu/si_dpm.c

4124

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);

sys/dev/drm/amd/amdgpu/si_dpm.c

4125

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);

sys/dev/drm/amd/amdgpu/si_dpm.c

4518

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,

sys/dev/drm/amd/amdgpu/si_dpm.c

4520

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,

sys/dev/drm/amd/amdgpu/si_dpm.c

4522

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,

sys/dev/drm/amd/amdgpu/si_dpm.c

4561

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,

sys/dev/drm/amd/amdgpu/si_dpm.c

5135

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,

sys/dev/drm/amd/amdgpu/si_dpm.c

5201

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,

sys/dev/drm/amd/amdgpu/si_dpm.c

5233

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);

sys/dev/drm/amd/amdgpu/si_dpm.c

5713

si_write_smc_soft_register(adev,

sys/dev/drm/amd/amdgpu/si_dpm.c

5797

if (si_write_smc_soft_register(adev,

sys/dev/drm/amd/amdgpu/si_dpm.c

5802

if (si_write_smc_soft_register(adev,

sys/dev/drm/amd/amdgpu/si_dpm.c

5807

if (si_write_smc_soft_register(adev,

sys/dev/drm/amd/amdgpu/si_dpm.c

6114

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);

sys/dev/drm/amd/amdgpu/si_dpm.c

6382

si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);

sys/dev/drm/radeon/si_dpm.c

1752

static int si_write_smc_soft_register(struct radeon_device *rdev,

sys/dev/drm/radeon/si_dpm.c

2724

ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);

sys/dev/drm/radeon/si_dpm.c

3372

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);

sys/dev/drm/radeon/si_dpm.c

3649

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);

sys/dev/drm/radeon/si_dpm.c

3666

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);

sys/dev/drm/radeon/si_dpm.c

3667

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);

sys/dev/drm/radeon/si_dpm.c

3668

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);

sys/dev/drm/radeon/si_dpm.c

3669

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);

sys/dev/drm/radeon/si_dpm.c

4059

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,

sys/dev/drm/radeon/si_dpm.c

4061

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,

sys/dev/drm/radeon/si_dpm.c

4063

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,

sys/dev/drm/radeon/si_dpm.c

4102

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,

sys/dev/drm/radeon/si_dpm.c

4675

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,

sys/dev/drm/radeon/si_dpm.c

4742

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,

sys/dev/drm/radeon/si_dpm.c

4774

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);

sys/dev/drm/radeon/si_dpm.c

5254

si_write_smc_soft_register(rdev,

sys/dev/drm/radeon/si_dpm.c

5340

if (si_write_smc_soft_register(rdev,

sys/dev/drm/radeon/si_dpm.c

5345

if (si_write_smc_soft_register(rdev,

sys/dev/drm/radeon/si_dpm.c

5350

if (si_write_smc_soft_register(rdev,

sys/dev/drm/radeon/si_dpm.c

5663

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);

sys/dev/drm/radeon/si_dpm.c

5927

si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);