Symbol: CP_ME1_PIPE0_INT_CNTL
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6665
WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4577
mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4583
mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
sys/dev/drm/radeon/cik.c
6895
WREG32(CP_ME1_PIPE0_INT_CNTL, 0);
sys/dev/drm/radeon/cik.c
7078
cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/drm/radeon/cik.c
7249
WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0);