sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6660

WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);

sys/dev/drm/amd/powerplay/inc/smu72_discrete.h

499

uint32_t CP_INT_CNTL;

sys/dev/drm/amd/powerplay/inc/smu73_discrete.h

495

uint32_t CP_INT_CNTL;

sys/dev/drm/amd/powerplay/inc/smu74_discrete.h

489

uint32_t CP_INT_CNTL;

sys/dev/drm/amd/powerplay/inc/smu75_discrete.h

501

uint32_t CP_INT_CNTL;

sys/dev/drm/radeon/evergreen.c

4453

WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);

sys/dev/drm/radeon/evergreen.c

4548

WREG32(CP_INT_CNTL, cp_int_cntl);

sys/dev/drm/radeon/ni.c

1406

WREG32(CP_INT_CNTL, cp_int_cntl);

sys/dev/drm/radeon/r600.c

3636

WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);

sys/dev/drm/radeon/r600.c

3887

WREG32(CP_INT_CNTL, cp_int_cntl);