sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

464

CP_HQD_PQ_CONTROL, QUEUE_SIZE);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4558

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4560

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4563

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4565

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4566

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4567

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4568

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2955

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2957

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2960

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2962

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2963

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2964

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2965

tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);

sys/dev/drm/radeon/cik.c

4684

mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);

sys/dev/drm/radeon/cik.c

4699

WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);