bin/mined/mined.h

296

void reset(LINE *head_line, int screen_y);

bin/mined/mined1.c

1401

reset(header->next, 0); /* Initialize pointers */

bin/mined/mined2.c

1435

reset(line, 0);

bin/mined/mined2.c

274

reset(header->next, 0);/* Reset top_line, etc. */

bin/mined/mined2.c

291

reset(proceed(tail->prev, -screenmax), screenmax);

bin/mined/mined2.c

563

reset(top_line, y); /* Reset pointers */

bin/mined/mined2.c

771

reset(top_line, y);

bin/mined/mined2.c

862

reset(top_line, y); /* Reset pointers */

bin/sh/eval.c

1025

shellparam.reset = 1;

bin/sh/eval.c

501

saveoptreset = shellparam.reset;

bin/sh/eval.c

516

shellparam.reset = saveoptreset;

bin/sh/eval.c

665

saveoptreset = shellparam.reset;

bin/sh/eval.c

676

shellparam.reset = saveoptreset;

bin/sh/eval.c

687

shellparam.reset = saveoptreset;

bin/sh/main.c

105

reset();

bin/sh/main.c

78

static void reset(void);

bin/sh/options.c

123

shellparam.reset = 1;

bin/sh/options.c

337

shellparam.reset = 1;

bin/sh/options.c

386

shellparam.reset = 1;

bin/sh/options.c

419

shellparam.reset = 1;

bin/sh/options.c

438

if (shellparam.reset == 1) {

bin/sh/options.c

456

shellparam.reset = 0;

bin/sh/options.h

41

unsigned char reset; /* if getopts has been reset */

crypto/libressl/crypto/hmac/hmac.c

116

if (reset) {

crypto/libressl/crypto/hmac/hmac.c

73

int i, j, reset = 0;

crypto/libressl/crypto/hmac/hmac.c

81

reset = 1;

crypto/libressl/crypto/hmac/hmac.c

89

reset = 1;

sbin/devd/devd.hh

145

virtual ~config() { reset(); }

sbin/devd/devd.hh

152

void reset();

sbin/ip6fw/ip6fw.c

682

fill_tcpflag(u_char *set, u_char *reset, char **vp)

sbin/ip6fw/ip6fw.c

703

d = reset;

sbin/ip6fw/ip6fw.c

722

fill_ip6opt(u_char *set, u_char *reset, char **vp)

sbin/ip6fw/ip6fw.c

730

d = reset;

sbin/restore/interactive.c

105

if (setjmp(reset) != 0) {

sbin/restore/interactive.c

53

static jmp_buf reset;

sbin/restore/interactive.c

759

longjmp(reset, 1);

sys/bus/u4b/controller/ohci.c

189

goto reset;

sys/bus/u4b/controller/ohci.c

193

reset:

sys/dev/disk/dm/delay/dm_target_delay.c

276

int reset = 0;

sys/dev/disk/dm/delay/dm_target_delay.c

289

if (reset == 0) {

sys/dev/disk/dm/delay/dm_target_delay.c

290

reset = 1;

sys/dev/disk/dm/delay/dm_target_delay.c

298

if (reset) {

sys/dev/disk/mpt/mpt.c

1177

pers->reset(mpt, ret);

sys/dev/disk/mpt/mpt.c

204

.reset = mpt_stdreset,

sys/dev/disk/mpt/mpt.c

225

.reset = mpt_core_ioc_reset,

sys/dev/disk/mpt/mpt.h

184

mpt_reset_handler_t *reset; /* Re-init after reset. */

sys/dev/disk/mpt/mpt_cam.c

182

.reset = mpt_cam_ioc_reset,

sys/dev/disk/mpt/mpt_raid.c

95

.reset = mpt_raid_ioc_reset,

sys/dev/disk/mpt/mpt_user.c

71

.reset = mpt_user_reset,

sys/dev/disk/nata/ata-all.h

480

void (*reset)(device_t dev);

sys/dev/disk/nata/ata-pci.c

556

ch->dma->reset = ata_pci_dmareset;

sys/dev/disk/nata/ata-pci.c

844

if (ch->dma->reset)

sys/dev/disk/nata/ata-pci.c

845

ch->dma->reset(dev);

sys/dev/disk/nata/ata-pci.c

850

if (ctlr->reset)

sys/dev/disk/nata/ata-pci.c

851

ctlr->reset(dev);

sys/dev/disk/nata/ata-pci.h

61

void (*reset)(device_t);

sys/dev/disk/nata/chipsets/ata-acerlabs.c

109

ctlr->reset = ata_ali_reset;

sys/dev/disk/nata/chipsets/ata-ahci.c

105

ctlr->reset = ata_ahci_reset;

sys/dev/disk/nata/chipsets/ata-intel.c

153

ctlr->reset = ata_intel_31244_reset;

sys/dev/disk/nata/chipsets/ata-intel.c

171

ctlr->reset = ata_intel_reset;

sys/dev/disk/nata/chipsets/ata-jmicron.c

104

ctlr->reset = ata_jmicron_reset;

sys/dev/disk/nata/chipsets/ata-jmicron.c

88

ctlr->reset = ata_generic_reset;

sys/dev/disk/nata/chipsets/ata-marvell.c

175

ctlr->reset = ata_marvell_edma_reset;

sys/dev/disk/nata/chipsets/ata-nvidia.c

179

ctlr->reset = ata_nvidia_reset;

sys/dev/disk/nata/chipsets/ata-promise.c

259

ctlr->reset = ata_promise_mio_reset;

sys/dev/disk/nata/chipsets/ata-promise.c

312

ctlr->reset = ata_promise_mio_reset;

sys/dev/disk/nata/chipsets/ata-promise.c

416

ch->dma->reset = ata_promise_dmareset;

sys/dev/disk/nata/chipsets/ata-siliconimage.c

117

ctlr->reset = ata_siiprb_reset;

sys/dev/disk/nata/chipsets/ata-siliconimage.c

170

ctlr->reset = ata_sii_reset;

sys/dev/disk/nata/chipsets/ata-sis.c

163

ctlr->reset = ata_sis_reset;

sys/dev/disk/nata/chipsets/ata-via.c

117

ctlr->reset = ata_via_reset;

sys/dev/drm/amd/amdgpu/amdgpu.h

1174

#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))

sys/dev/drm/amd/amdgpu/amdgpu.h

643

int (*reset)(struct amdgpu_device *adev);

sys/dev/drm/amd/amdgpu/cik.c

1753

.reset = &cik_asic_reset,

sys/dev/drm/amd/amdgpu/soc15.c

609

.reset = &soc15_asic_reset,

sys/dev/drm/amd/amdgpu/vi.c

951

.reset = &vi_asic_reset,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3030

.reset = dm_crtc_reset_state,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3235

.reset = amdgpu_dm_connector_funcs_reset,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3479

.reset = dm_drm_plane_reset,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3681

if (aplane->base.funcs->reset)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3682

aplane->base.funcs->reset(&aplane->base);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3721

if (acrtc->base.funcs->reset)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3722

acrtc->base.funcs->reset(&acrtc->base);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4105

if (aconnector->base.funcs->reset)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4106

aconnector->base.funcs->reset(&aconnector->base);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

203

.reset = amdgpu_dm_connector_funcs_reset,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

611

void hubbub1_soft_reset(struct hubbub *hubbub, bool reset)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

613

uint32_t reset_en = reset ? 1 : 0;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.h

216

void hubbub1_soft_reset(struct hubbub *hubbub, bool reset);

sys/dev/drm/drm_mode_config.c

184

if (plane->funcs->reset)

sys/dev/drm/drm_mode_config.c

185

plane->funcs->reset(plane);

sys/dev/drm/drm_mode_config.c

188

if (crtc->funcs->reset)

sys/dev/drm/drm_mode_config.c

189

crtc->funcs->reset(crtc);

sys/dev/drm/drm_mode_config.c

192

if (encoder->funcs->reset)

sys/dev/drm/drm_mode_config.c

193

encoder->funcs->reset(encoder);

sys/dev/drm/drm_mode_config.c

197

if (connector->funcs->reset)

sys/dev/drm/drm_mode_config.c

198

connector->funcs->reset(connector);

sys/dev/drm/drm_simple_kms_helper.c

120

.reset = drm_atomic_helper_crtc_reset,

sys/dev/drm/drm_simple_kms_helper.c

204

.reset = drm_atomic_helper_plane_reset,

sys/dev/drm/i915/i915_drv.c

2323

if (i915_modparams.reset)

sys/dev/drm/i915/i915_drv.h

3575

bool reset);

sys/dev/drm/i915/i915_gem.c

3448

request = engine->reset.prepare(engine);

sys/dev/drm/i915/i915_gem.c

3583

engine->reset.reset(engine, request);

sys/dev/drm/i915/i915_gem.c

3631

engine->reset.finish(engine);

sys/dev/drm/i915/i915_params.c

73

i915_param_named_unsafe(reset, int, 0600,

sys/dev/drm/i915/i915_params.h

56

param(int, reset, 2) \

sys/dev/drm/i915/i915_request.c

1288

DEFINE_WAIT_FUNC(reset, default_wake_function);

sys/dev/drm/i915/i915_request.c

1310

add_wait_queue(errq, &reset);

sys/dev/drm/i915/i915_request.c

1414

remove_wait_queue(errq, &reset);

sys/dev/drm/i915/intel_crt.c

924

.reset = intel_crt_reset,

sys/dev/drm/i915/intel_ddi.c

3521

.reset = intel_dp_encoder_reset,

sys/dev/drm/i915/intel_dp.c

5651

.reset = intel_dp_encoder_reset,

sys/dev/drm/i915/intel_dpio_phy.c

736

bool reset)

sys/dev/drm/i915/intel_dpio_phy.c

745

if (reset)

sys/dev/drm/i915/intel_dpio_phy.c

753

if (reset)

sys/dev/drm/i915/intel_dpio_phy.c

762

if (reset)

sys/dev/drm/i915/intel_dpio_phy.c

771

if (reset)

sys/dev/drm/i915/intel_engine_cs.c

1045

if (engine->reset.reset)

sys/dev/drm/i915/intel_engine_cs.c

1046

engine->reset.reset(engine, NULL);

sys/dev/drm/i915/intel_guc_submission.c

1271

engine->reset.prepare = guc_reset_prepare;

sys/dev/drm/i915/intel_lrc.c

2333

engine->reset.prepare = execlists_reset_prepare;

sys/dev/drm/i915/intel_lrc.c

2355

engine->reset.prepare = execlists_reset_prepare;

sys/dev/drm/i915/intel_lrc.c

2356

engine->reset.reset = execlists_reset;

sys/dev/drm/i915/intel_lrc.c

2357

engine->reset.finish = execlists_reset_finish;

sys/dev/drm/i915/intel_ringbuffer.c

2216

engine->reset.prepare = reset_prepare;

sys/dev/drm/i915/intel_ringbuffer.c

2217

engine->reset.reset = reset_ring;

sys/dev/drm/i915/intel_ringbuffer.c

2218

engine->reset.finish = reset_finish;

sys/dev/drm/i915/intel_ringbuffer.h

454

void (*reset)(struct intel_engine_cs *engine,

sys/dev/drm/i915/intel_ringbuffer.h

457

} reset;

sys/dev/drm/i915/intel_uncore.c

2169

if (!i915_modparams.reset)

sys/dev/drm/i915/intel_uncore.c

2191

reset_func reset = intel_get_gpu_reset(dev_priv);

sys/dev/drm/i915/intel_uncore.c

2237

if (reset) {

sys/dev/drm/i915/intel_uncore.c

2238

ret = reset(dev_priv, engine_mask, retry);

sys/dev/drm/i915/intel_uncore.c

2260

i915_modparams.reset >= 2);

sys/dev/drm/include/drm/drm_connector.h

549

void (*reset)(struct drm_connector *connector);

sys/dev/drm/include/drm/drm_crtc.h

379

void (*reset)(struct drm_crtc *crtc);

sys/dev/drm/include/drm/drm_encoder.h

48

void (*reset)(struct drm_encoder *encoder);

sys/dev/drm/include/drm/drm_plane.h

299

void (*reset)(struct drm_plane *plane);

sys/dev/netif/bge/if_bge.c

2755

uint32_t cachesize, command, reset, mac_mode, mac_mode_mask;

sys/dev/netif/bge/if_bge.c

2817

reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);

sys/dev/netif/bge/if_bge.c

2832

reset |= (1<<29);

sys/dev/netif/bge/if_bge.c

2852

reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;

sys/dev/netif/bge/if_bge.c

2855

write_op(sc, BGE_MISC_CFG, reset);

sys/dev/netif/bnx/if_bnx.c

2573

uint32_t cachesize, command, reset, mac_mode, mac_mode_mask;

sys/dev/netif/bnx/if_bnx.c

2618

reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);

sys/dev/netif/bnx/if_bnx.c

2632

reset |= (1<<29);

sys/dev/netif/bnx/if_bnx.c

2652

reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;

sys/dev/netif/bnx/if_bnx.c

2655

write_op(sc, BGE_MISC_CFG, reset);

sys/dev/netif/bnx/if_bnx.c

2949

int reset = 0;

sys/dev/netif/bnx/if_bnx.c

2957

reset = 1;

sys/dev/netif/bnx/if_bnx.c

2964

reset = 1;

sys/dev/netif/bnx/if_bnx.c

2971

reset = 1;

sys/dev/netif/bnx/if_bnx.c

2978

reset = 1;

sys/dev/netif/bnx/if_bnx.c

2981

if (reset) {

sys/dev/netif/ig_hal/e1000_80003es2lan.c

116

phy->ops.reset = e1000_phy_hw_reset_generic;

sys/dev/netif/ig_hal/e1000_82540.c

83

phy->ops.reset = e1000_phy_hw_reset_generic;

sys/dev/netif/ig_hal/e1000_82541.c

103

phy->ops.reset = e1000_phy_hw_reset_82541;

sys/dev/netif/ig_hal/e1000_82543.c

1074

ret_val = hw->phy.ops.reset(hw);

sys/dev/netif/ig_hal/e1000_82543.c

111

phy->ops.reset = (hw->mac.type == e1000_82543)

sys/dev/netif/ig_hal/e1000_82543.c

125

ret_val = phy->ops.reset(hw);

sys/dev/netif/ig_hal/e1000_82571.c

111

phy->ops.reset = e1000_phy_hw_reset_generic;

sys/dev/netif/ig_hal/e1000_82575.c

1582

ret_val = hw->phy.ops.reset(hw);

sys/dev/netif/ig_hal/e1000_82575.c

194

phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;

sys/dev/netif/ig_hal/e1000_82575.c

197

phy->ops.reset = e1000_phy_hw_reset_generic;

sys/dev/netif/ig_hal/e1000_api.c

1151

if (hw->phy.ops.reset)

sys/dev/netif/ig_hal/e1000_api.c

1152

return hw->phy.ops.reset(hw);

sys/dev/netif/ig_hal/e1000_hw.h

782

s32 (*reset)(struct e1000_hw *);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1524

hw->phy.ops.reset(hw);

sys/dev/netif/ig_hal/e1000_ich8lan.c

468

phy->ops.reset = e1000_phy_hw_reset_ich8lan;

sys/dev/netif/ig_hal/e1000_ich8lan.c

5488

hw->phy.ops.reset(hw);

sys/dev/netif/ig_hal/e1000_ich8lan.c

558

phy->ops.reset = e1000_phy_hw_reset_ich8lan;

sys/dev/netif/ig_hal/e1000_phy.c

1062

ret_val = hw->phy.ops.reset(hw);

sys/dev/netif/ig_hal/e1000_phy.c

1375

ret_val = hw->phy.ops.reset(hw);

sys/dev/netif/ig_hal/e1000_phy.c

90

phy->ops.reset = e1000_null_ops_generic;

sys/dev/netif/ix/if_ix.c

3416

ret = hw->phy.ops.reset(hw);

sys/dev/netif/ix/if_ix.c

3479

err = hw->phy.ops.reset(hw);

sys/dev/netif/ix/ixgbe_82598.c

218

phy->ops.reset = ixgbe_reset_phy_nl;

sys/dev/netif/ix/ixgbe_82598.c

871

hw->phy.ops.reset(hw);

sys/dev/netif/ix/ixgbe_82599.c

1069

if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)

sys/dev/netif/ix/ixgbe_82599.c

1070

hw->phy.ops.reset(hw);

sys/dev/netif/ix/ixgbe_82599.c

149

hw->phy.ops.reset = NULL;

sys/dev/netif/ix/ixgbe_82599.c

183

hw->phy.ops.reset = NULL;

sys/dev/netif/ix/ixgbe_api.c

498

status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),

sys/dev/netif/ix/ixgbe_phy.c

260

phy->ops.reset = ixgbe_reset_phy_generic;

sys/dev/netif/ix/ixgbe_type.h

4005

s32 (*reset)(struct ixgbe_hw *);

sys/dev/netif/ix/ixgbe_x540.c

84

phy->ops.reset = NULL;

sys/dev/netif/ix/ixgbe_x550.c

1623

hw->phy.ops.reset = NULL;

sys/dev/netif/ix/ixgbe_x550.c

2331

phy->ops.reset = NULL;

sys/dev/netif/ix/ixgbe_x550.c

2348

phy->ops.reset = NULL;

sys/dev/netif/ix/ixgbe_x550.c

2370

phy->ops.reset = ixgbe_reset_phy_t_X550em;

sys/dev/netif/ix/ixgbe_x550.c

2377

phy->ops.reset = ixgbe_reset_phy_fw;

sys/dev/netif/ix/ixgbe_x550.c

2480

if (!hw->phy.reset_disable && hw->phy.ops.reset) {

sys/dev/netif/ix/ixgbe_x550.c

2481

if (hw->phy.ops.reset(hw) == IXGBE_ERR_OVERTEMP)

sys/dev/netif/oce/oce_sysctl.c

1299

int rc = 0, reset = 0;

sys/dev/netif/oce/oce_sysctl.c

1313

rc = oce_mbox_get_pport_stats(sc, &sc->stats_mem, reset);

sys/dev/raid/hpt27xx/ldm.h

310

void (*reset)(PVDEV vd);

sys/dev/raid/hptrr/ldm.h

306

void (*reset)(PVDEV vd);

sys/dev/sound/pcm/channel.c

129

chn_vpc_proc(int reset, int db)

sys/dev/sound/pcm/channel.c

146

if (reset != 0)

sys/dev/virtual/vmware/vmxnet3/if_vmx.c

1876

int reset;

sys/dev/virtual/vmware/vmxnet3/if_vmx.c

1880

reset = 0;

sys/dev/virtual/vmware/vmxnet3/if_vmx.c

1895

reset = 1;

sys/dev/virtual/vmware/vmxnet3/if_vmx.c

1911

if (reset != 0) {

sys/netgraph/async/ng_async.c

543

goto reset;

sys/netgraph/async/ng_async.c

549

goto reset;

sys/netgraph/async/ng_async.c

562

goto reset;

sys/netgraph/async/ng_async.c

572

reset:

sys/netgraph7/async/ng_async.c

569

goto reset;

sys/netgraph7/async/ng_async.c

575

goto reset;

sys/netgraph7/async/ng_async.c

588

goto reset;

sys/netgraph7/async/ng_async.c

603

reset:

test/sysperf/randread.c

115

if (pdata->reset) {

test/sysperf/randread.c

121

pdata->reset = 0;

test/sysperf/randread.c

172

pdata[i].reset = 1;

test/sysperf/randread.c

33

int reset;

tools/tools/ath/athstats/athstats.c

659

case S_ANI_RESET: ANISTAT(reset);

tools/tools/ath/athstats/athstats.c

879

case S_ANI_RESET: ANISTAT(reset);

usr.bin/dsynth/dsynth.h

493

void (*reset)(void);

usr.bin/dsynth/html.c

517

.reset = HtmlReset,

usr.bin/dsynth/monitor.c

180

.reset = MonitorReset,

usr.bin/dsynth/monitor.c

238

NCursesRunStats.reset();

usr.bin/dsynth/ncurses.c

363

.reset = NCursesReset,

usr.bin/dsynth/runstats.c

82

rs->reset();

usr.bin/ktrdump/ktrdump.c

55

int reset;

usr.bin/ktrdump/ktrdump.c

850

it->reset = 1;

usr.bin/ktrdump/ktrdump.c

913

if (kbuf->reset) {

usr.bin/ktrdump/ktrdump.c

915

kbuf->reset = 0;

usr.bin/mail/lex.c

546

reset(0);

usr.bin/mail/lex.c

566

reset(0);

usr.bin/mail/quit.c

430

reset(0);

usr.bin/mail/quit.c

437

reset(0);

usr.bin/mail/quit.c

448

reset(0);

usr.bin/mail/quit.c

457

reset(0);

usr.bin/mail/quit.c

468

reset(0);

usr.bin/mail/quit.c

481

reset(0);

usr.bin/patch/util.c

298

set_signals(int reset)

usr.bin/patch/util.c

302

if (!reset) {