reg_write
reg_write(sc, IG4_REG_INTR_MASK, val);
reg_write(sc, IG4_REG_I2C_EN, ctl);
reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_STOP);
reg_write(sc, IG4_REG_CTL, ctl);
reg_write(sc, IG4_REG_TAR_ADD, tar);
reg_write(sc, IG4_REG_DATA_CMD, last);
reg_write(sc, IG4_REG_DATA_CMD, last);
reg_write(sc, IG4_REG_DATA_CMD, last);
reg_write(sc, IG4_REG_DATA_CMD, last);
reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD |
reg_write(sc, IG4_REG_GENERAL, v);
reg_write(sc, IG4_REG_FS_SCL_HCNT, v);
reg_write(sc, IG4_REG_FS_SCL_LCNT, v);
reg_write(sc, IG4_REG_INTR_MASK, 0);
reg_write(sc, IG4_REG_SS_SCL_HCNT, 100);
reg_write(sc, IG4_REG_SS_SCL_LCNT, 125);
reg_write(sc, IG4_REG_FS_SCL_HCNT, 100);
reg_write(sc, IG4_REG_FS_SCL_LCNT, 125);
reg_write(sc, IG4_REG_SDA_HOLD, 1);
reg_write(sc, IG4_REG_RX_TL, 0);
reg_write(sc, IG4_REG_CTL,
reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);
reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);
reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);
reg_write(sc, IG4_REG_INTR_MASK, 0);
reg_write(sc, IG4_REG_DATA_CMD, cmd);
reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD);
atom_card_info->reg_write = cail_reg_write;
gctx->card->reg_write(gctx->card, idx,
gctx->card->reg_write(gctx->card, idx, val);
void (* reg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */
gctx->card->reg_write(gctx->card, idx,
gctx->card->reg_write(gctx->card, idx, val);
void (* reg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */
atom_card_info->reg_write = cail_reg_write;