reg_read
device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg))
reg_read(sc, IG4_REG_CLR_INTR);
v = reg_read(sc, IG4_REG_ENABLE_STATUS);
v = reg_read(sc, IG4_REG_I2C_STA);
v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;
c = (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
ctl = reg_read(sc, IG4_REG_CTL);
reg_read(sc, IG4_REG_CLR_TX_ABORT);
last = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
v = reg_read(sc, IG4_REG_COMP_TYPE);
v = reg_read(sc, IG4_REG_COMP_PARAM1);
v = reg_read(sc, IG4_REG_GENERAL);
v = reg_read(sc, IG4_REG_GENERAL);
v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);
v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);
v = reg_read(sc, IG4_REG_COMP_VER);
v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
v = reg_read(sc, IG4_REG_FS_SCL_HCNT);
v = reg_read(sc, IG4_REG_FS_SCL_LCNT);
v = reg_read(sc, IG4_REG_SDA_HOLD);
v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
reg_read(sc, IG4_REG_CLR_INTR);
reg_read(sc, IG4_REG_CLR_INTR);
status = reg_read(sc, IG4_REG_I2C_STA);
(uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
status = reg_read(sc, IG4_REG_I2C_STA);
atom_card_info->reg_read = cail_reg_read;
val = gctx->card->reg_read(gctx->card, idx);
uint32_t (* reg_read)(struct card_info *, uint32_t); /* filled by driver */
val = gctx->card->reg_read(gctx->card, idx);
uint32_t (* reg_read)(struct card_info *, uint32_t); /* filled by driver */
atom_card_info->reg_read = cail_reg_read;