sys/dev/drm/amd/display/dc/core/dc_link.c

1494

settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;

sys/dev/drm/amd/display/dc/core/dc_link.c

1506

settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;

sys/dev/drm/amd/display/dc/core/dc_link.c

1518

settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;

sys/dev/drm/amd/display/dc/core/dc_link.c

1530

settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;

sys/dev/drm/amd/display/dc/core/dc_link.c

1548

if (settings->reg_num > 9)

sys/dev/drm/amd/display/dc/core/dc_link.c

1553

for (i = 0; i < settings->reg_num; i++) {

sys/dev/drm/amd/display/dc/core/dc_link.c

1613

for (i = 0; i < settings->reg_num; i++) {

sys/dev/drm/amd/display/dc/dm_services.h

178

#define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\

sys/dev/drm/amd/display/dc/dm_services.h

181

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\

sys/dev/drm/amd/display/dc/dm_services.h

182

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)

sys/dev/drm/amd/display/dc/dm_services.h

184

#define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\

sys/dev/drm/amd/display/dc/dm_services.h

188

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\

sys/dev/drm/amd/display/dc/dm_services.h

189

block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

100

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

101

.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

106

.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

109

.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

112

#define pflip_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

113

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

114

.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

120

.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

123

.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

127

#define vupdate_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

128

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

129

.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

135

.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

143

#define vblank_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

144

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

145

.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

151

.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

157

.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

165

#define i2c_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

166

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

168

#define dp_sink_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

169

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

171

#define gpio_pad_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

172

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

174

#define dc_underflow_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

175

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

84

#define hpd_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

85

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

86

.enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

92

.ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

95

.status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\

sys/dev/drm/amd/display/dc/irq/dce110/irq_service_dce110.c

99

#define hpd_rx_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

101

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

103

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

104

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

106

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

108

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

110

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

112

#define hpd_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

113

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

114

IRQ_REG_ENTRY(HPD, reg_num,\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

117

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

121

#define hpd_rx_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

122

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

123

IRQ_REG_ENTRY(HPD, reg_num,\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

126

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

129

#define pflip_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

130

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

131

IRQ_REG_ENTRY(DCP, reg_num, \

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

134

.status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

138

#define vupdate_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

139

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

140

IRQ_REG_ENTRY(CRTC, reg_num,\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

146

#define vblank_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

147

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

148

IRQ_REG_ENTRY(CRTC, reg_num,\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

152

.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

160

#define i2c_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

161

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

163

#define dp_sink_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

164

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

166

#define gpio_pad_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

167

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

169

#define dc_underflow_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

170

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

98

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

sys/dev/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

99

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

103

#define hpd_rx_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

104

[DC_IRQ_SOURCE_HPD6 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

105

.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

110

.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

113

.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

117

#define pflip_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

118

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

119

.enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

125

.ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

128

.status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

132

#define vupdate_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

133

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

134

.enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

140

.ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

148

#define vblank_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

149

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

150

.enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

156

.ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

162

.src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

170

#define i2c_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

171

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

173

#define dp_sink_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

174

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

176

#define gpio_pad_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

177

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

179

#define dc_underflow_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

180

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

88

#define hpd_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

89

[DC_IRQ_SOURCE_INVALID + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

90

.enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

96

.ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\

sys/dev/drm/amd/display/dc/irq/dce80/irq_service_dce80.c

99

.status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

168

#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

169

.enable_reg = SRI(reg1, block, reg_num),\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

171

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

173

block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

174

~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

176

.ack_reg = SRI(reg2, block, reg_num),\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

178

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

180

block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

182

#define hpd_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

183

[DC_IRQ_SOURCE_HPD1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

184

IRQ_REG_ENTRY(HPD, reg_num,\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

187

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

191

#define hpd_rx_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

192

[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

193

IRQ_REG_ENTRY(HPD, reg_num,\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

196

.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

199

#define pflip_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

200

[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

201

IRQ_REG_ENTRY(HUBPREQ, reg_num,\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

207

#define vupdate_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

208

[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

209

IRQ_REG_ENTRY(OTG, reg_num,\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

215

#define vblank_int_entry(reg_num)\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

216

[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

217

IRQ_REG_ENTRY(OTG, reg_num,\

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

228

#define i2c_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

229

[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

231

#define dp_sink_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

232

[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

234

#define gpio_pad_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

235

[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

237

#define dc_underflow_int_entry(reg_num) \

sys/dev/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

238

[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()

sys/dev/drm/amd/display/include/grph_object_ctrl_defs.h

275

unsigned char reg_num;

sys/dev/drm/radeon/evergreen.c

4139

u32 dws, data, i, j, k, reg_num;

sys/dev/drm/radeon/evergreen.c

4281

reg_num = cs_data[i].section[j].reg_count;

sys/dev/drm/radeon/evergreen.c

4290

data = 0x08000000 | (reg_num * 4);

sys/dev/drm/radeon/evergreen.c

4294

for (k = 0; k < reg_num; k++) {

sys/dev/drm/radeon/evergreen.c

4298

reg_list_mc_addr += reg_num * 4;

sys/dev/drm/radeon/evergreen.c

4299

reg_list_blk_index += reg_num;