read_config
read_config(basename(tokens[1]), RULES_FILE);
error = read_config("ruletab", RULETAB_FILE);
read_config(rt->rule_file, RULES_FILE);
read_config(config_name, RULES_FILE);
int read_config(const char *, int);
static int read_config(char *config_file);
if (!read_config(f_flag))
host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
*busnum = read_config(bus, slot, func, 0x4a, 1);
*busnum = read_config(bus, 0x10, func, 0xd0, 1);
*busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
*busnum = read_config(bus, 0x10, func, 0xd3, 1);
*busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
*busnum = read_config(bus, slot, func, 0x44, 1);
*busnum = read_config(bus, slot, func, 0xc8, 1);
int host_pcib_get_busno(pci_read_config_fn read_config, int bus,
if (read_config(config)) {
static int read_config(FILE *);
ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2);
status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4);
command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2);
reg = read_config(fd, &p->pc_sel,
reg = read_config(fd, &p->pc_sel,
length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1);
version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA,
fvec = read_config(fd, &p->pc_sel, ptr +
fvec = read_config(fd, &p->pc_sel, ptr +
debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2);
id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4);
flags = read_config(fd, &p->pc_sel, ptr + PCIER_CAPABILITY, 2);
cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVCAP, 4);
ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVCTRL, 2);
cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVCAP2, 4);
ctl = read_config(fd, &p->pc_sel,
cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINKCAP, 4);
sta = read_config(fd, &p->pc_sel, ptr+ PCIER_LINKSTAT, 2);
ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINKCTRL, 2);
cap = read_config(fd, &p->pc_sel, ptr + PCIER_SLOTCAP, 4);
sta = read_config(fd, &p->pc_sel, ptr + PCIER_SLOTSTA, 2);
ctl = read_config(fd, &p->pc_sel, ptr + PCIER_SLOTCTL, 2);
ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2);
val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4);
val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4);
cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1);
sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2);
ptr = read_config(fd, &p->pc_sel, ptr, 1);
cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2);
ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4);
mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4);
sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4);
cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4);
low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4);
high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4);
ecap = read_config(fd, &p->pc_sel, ptr, 4);
status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4);
ecap = read_config(fd, &p->pc_sel, ptr, 4);
command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4);
sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
ptr = read_config(fd, &p->pc_sel, ptr, 1);
cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
ecap = read_config(fd, &p->pc_sel, ptr, 4);
ecap = read_config(fd, &p->pc_sel, ptr, 4);
sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
sta = read_config(fd, &p->pc_sel, pcie + PCIER_DEVSTS, 2);
mask = read_config(fd, &p->pc_sel, aer + PCIR_AER_UC_STATUS, 4);
severity = read_config(fd, &p->pc_sel, aer + PCIR_AER_UC_SEVERITY, 4);
mask = read_config(fd, &p->pc_sel, aer + PCIR_AER_COR_STATUS, 4);
secbus = read_config(fd, &p->pc_sel, secreg, 1);
subbus = read_config(fd, &p->pc_sel, subreg, 1);
val = read_config(fd, &p->pc_sel, PCIR_IOBASEL_1, 1);
if (val != 0 || read_config(fd, &p->pc_sel, PCIR_IOLIMITL_1, 1) != 0) {
read_config(fd, &p->pc_sel, PCIR_IOBASEH_1, 2),
read_config(fd, &p->pc_sel, PCIR_IOLIMITH_1, 2),
read_config(fd, &p->pc_sel, PCIR_IOLIMITL_1, 1));
read_config(fd, &p->pc_sel, PCIR_IOLIMITL_1, 1));
read_config(fd, &p->pc_sel, PCIR_MEMBASE_1, 2));
read_config(fd, &p->pc_sel, PCIR_MEMLIMIT_1, 2));
val = read_config(fd, &p->pc_sel, PCIR_PMBASEL_1, 2);
if (val != 0 || read_config(fd, &p->pc_sel, PCIR_PMLIMITL_1, 2) != 0) {
read_config(fd, &p->pc_sel, PCIR_PMBASEH_1, 4),
read_config(fd, &p->pc_sel, PCIR_PMLIMITH_1, 4),
read_config(fd, &p->pc_sel, PCIR_PMLIMITL_1, 2));
read_config(fd, &p->pc_sel, PCIR_PMLIMITL_1, 2));
bctl = read_config(fd, &p->pc_sel, PCIR_BRIDGECTL_1, 2);
PCI_CBBMEMBASE(read_config(fd, &p->pc_sel, basereg, 4)),
PCI_CBBMEMLIMIT(read_config(fd, &p->pc_sel, limitreg, 4)));
val = read_config(fd, &p->pc_sel, basereg, 2);
base = PCI_CBBIOBASE(read_config(fd, &p->pc_sel, basereg, 4));
limit = PCI_CBBIOBASE(read_config(fd, &p->pc_sel, limitreg, 4));
limit = PCI_CBBIOBASE(read_config(fd, &p->pc_sel, limitreg, 2));
bctl = read_config(fd, &p->pc_sel, PCIR_BRIDGECTL_2, 2);
printf("%0*x", width*2, read_config(fd, sel, reg, width));
uint32_t read_config(int fd, struct pcisel *sel, long reg, int width);