rdmsr
u_int64_t rdmsr(u_int msr);
aperf = rdmsr(MSR_APERF);
mperf = rdmsr(MSR_MPERF);
v64 = rdmsr(0x017B);
b = rdmsr(msr);
b = rdmsr(msr);
val = rdmsr(MSR_RAPL_POWER_UNIT);
(rdmsr(MSR_PLATFORM_ENERGY_COUNTER) & 0xffffffffU) != 0) {
sens->energy = rdmsr(sens->msr) & 0xffffffffU;
a = rdmsr(sens->msr) & 0xffffffffU;
msr = rdmsr(MSR_BIOS_SIGN);
msr = rdmsr(MSR_IA32_EXT_CONFIG);
*msr = rdmsr(MSR_THERM_STATUS);
*pkg_msr = rdmsr(MSR_PKG_THERM_STATUS);
hint = rdmsr(INTEL_MSR_PERF_BIAS);
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
(status) = rdmsr(MSR_AMDK7_FIDVID_STATUS); \
val = rdmsr(MSR_HV_TIME_REF_COUNT);
hc_orig = rdmsr(MSR_HV_HYPERCALL);
hc = rdmsr(MSR_HV_HYPERCALL);
hc = rdmsr(MSR_HV_HYPERCALL);
return (rdmsr(MSR_HV_TIME_REF_COUNT));
psc->vcpuid = rdmsr(MSR_HV_VP_INDEX);
orig = rdmsr(MSR_HV_SIMP);
orig = rdmsr(MSR_HV_SIEFP);
orig = rdmsr(sint);
orig = rdmsr(sint);
orig = rdmsr(MSR_HV_SCONTROL);
val = rdmsr(MSR_HV_STIMER0_CONFIG);
orig = rdmsr(MSR_HV_SCONTROL);
orig = rdmsr(sint);
orig = rdmsr(sint);
orig = rdmsr(MSR_HV_SIMP);
orig = rdmsr(MSR_HV_SIEFP);
return (rdmsr(MSR_HV_TIME_REF_COUNT)); \
orig = rdmsr(MSR_HV_REFERENCE_TSC);
val = rdmsr(MSR_HV_REFERENCE_TSC);
struct nvmm_x86_exit_rdmsr rdmsr;
if (exit->u.rdmsr.msr == MSR_EFER) {
if (exit->u.rdmsr.msr == MSR_NB_CFG) {
if (msr_ignore_list[i] != exit->u.rdmsr.msr)
exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
exit->u.rdmsr.npc = cpudata->vmcb->ctrl.nrip;
cpudata->hstate.fsbase = rdmsr(MSR_FSBASE);
cpudata->hstate.kernelgsbase = rdmsr(MSR_KERNELGSBASE);
msr = rdmsr(MSR_VM_CR);
msr = rdmsr(MSR_VM_CR);
msr = rdmsr(MSR_EFER);
svm_global_hstate.star = rdmsr(MSR_STAR);
svm_global_hstate.lstar = rdmsr(MSR_LSTAR);
svm_global_hstate.cstar = rdmsr(MSR_CSTAR);
svm_global_hstate.sfmask = rdmsr(MSR_SFMASK);
if (exit->u.rdmsr.msr == MSR_CR_PAT) {
if (exit->u.rdmsr.msr == MSR_IA32_MISC_ENABLE) {
if (exit->u.rdmsr.msr == MSR_IA32_ARCH_CAPABILITIES) {
val = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
if (msr_ignore_list[i] != exit->u.rdmsr.msr)
exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
exit->u.rdmsr.npc = rip + inslen;
vmx_vmwrite(VMCS_HOST_FS_BASE, rdmsr(MSR_FSBASE));
cpudata->hstate.kernelgsbase = rdmsr(MSR_KERNELGSBASE);
vmx_vmwrite(VMCS_HOST_GS_BASE, rdmsr(MSR_GSBASE));
vmx_vmwrite(VMCS_HOST_IA32_PAT, rdmsr(MSR_CR_PAT));
vmx_vmwrite(VMCS_HOST_IA32_EFER, rdmsr(MSR_EFER));
cpudata->gmsr_misc_enable = rdmsr(MSR_IA32_MISC_ENABLE);
basic = rdmsr(MSR_IA32_VMX_BASIC);
val = rdmsr(msr_ctls);
true_val = rdmsr(msr_true_ctls);
basic = rdmsr(MSR_IA32_VMX_BASIC);
val = rdmsr(msr_ctls);
true_val = rdmsr(msr_true_ctls);
msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
msr = rdmsr(MSR_IA32_VMX_BASIC);
vmx_cr0_fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0) & ~(CR0_PG|CR0_PE);
vmx_cr0_fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1) | (CR0_PG|CR0_PE);
vmx_cr4_fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0);
vmx_cr4_fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1);
msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);
msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);
vmx_global_hstate.star = rdmsr(MSR_STAR);
vmx_global_hstate.lstar = rdmsr(MSR_LSTAR);
vmx_global_hstate.cstar = rdmsr(MSR_CSTAR);
vmx_global_hstate.sfmask = rdmsr(MSR_SFMASK);
msr = rdmsr(MSR_IA32_VMX_BASIC);
pstate = rdmsr(msr);
sval = rdmsr(AMD1X_MSR_PSTATE_ST) & AMD_MSR_PSTATE_CSR_MASK;
misc_enable = rdmsr(INTEL_MSR_MISC_ENABLE);
misc_enable = rdmsr(INTEL_MSR_MISC_ENABLE);
ctl = rdmsr(INTEL_MSR_PERF_CTL);
sval = rdmsr(INTEL_MSR_PERF_STATUS) & INTEL_MSR_PERF_MASK;
apic_base = rdmsr(MSR_APICBASE);
apic_base = rdmsr(MSR_APICBASE);
apic_base = rdmsr(MSR_APICBASE);
msr = rdmsr(0xc0010055);
#define LAPIC_MSR_READ(msr) rdmsr((msr))
msrv = rdmsr(msr);
msrv = rdmsr(msr);
msrv = rdmsr(msr);
msrv = rdmsr(msr);
msrv = rdmsr(msr + 1);
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE);
omsrv = rdmsr(msr);
omsrv = rdmsr(msr);
omsrv = rdmsr(msr);
omsrv = rdmsr(msr);
wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
mtrrcap = rdmsr(MSR_MTRRcap);
mtrrdef = rdmsr(MSR_MTRRdefType);
status = rdmsr(AMD0F_MSR_FIDVID_STATUS);
status = rdmsr(AMD0F_MSR_FIDVID_STATUS);
(status) = rdmsr(AMD0F_MSR_FIDVID_STATUS); \
status = rdmsr(AMD0F_MSR_FIDVID_STATUS);
msr = rdmsr(MSR_AMD_VM_CR);
val = rdmsr(true_msr);
val = rdmsr(msr);
msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
basic = rdmsr(MSR_VMX_BASIC);
msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
msreg = rdmsr(0x110B);
msreg = rdmsr(0x1107);
msreg = rdmsr(0x1107);
msreg = rdmsr(0x1107);
msreg = rdmsr(0x1107);
msr = rdmsr(MSR_AMD_DE_CFG);
msr = rdmsr(0xc001001f);
msr = rdmsr(0xc001102a);
msr = rdmsr(0xc0011020);
msr = rdmsr(MSR_EFER) | EFER_NXE;
msr = rdmsr(MSR_EFER) | EFER_SCE;
msr = rdmsr(MSR_EFER) | EFER_SCE;
if ((rdmsr(MSR_APICBASE) & APICBASE_PHYSADDR) == 0xfee00000) {
uint64_t rdmsr(uint64_t);
if (exit->u.rdmsr.msr != MSR_APICBASE) {
state->gprs[NVMM_X64_GPR_RIP] = exit->u.rdmsr.npc;