sys/dev/drm/radeon/evergreen_cs.c

1150

track->db_depth_control = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1168

track->db_z_info = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1196

track->db_s_info = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1200

track->db_depth_view = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1204

track->db_depth_size = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1208

track->db_depth_slice = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1218

track->db_z_read_offset = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1230

track->db_z_write_offset = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1242

track->db_s_read_offset = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1254

track->db_s_write_offset = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1260

track->vgt_strmout_config = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1264

track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1278

track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;

sys/dev/drm/radeon/evergreen_cs.c

1289

track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;

sys/dev/drm/radeon/evergreen_cs.c

1302

track->cb_target_mask = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1306

track->cb_shader_mask = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1315

tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;

sys/dev/drm/radeon/evergreen_cs.c

1324

tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;

sys/dev/drm/radeon/evergreen_cs.c

1336

track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1344

track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1356

track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1374

track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1396

track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1404

track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1416

track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1425

track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1532

track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1543

track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1560

track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1576

track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1588

track->htile_offset = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1595

track->htile_surface = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1737

track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;

sys/dev/drm/radeon/evergreen_cs.c

1785

idx_value = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

1799

tmp = radeon_get_ib_value(p, idx + 1);

sys/dev/drm/radeon/evergreen_cs.c

1865

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

1900

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

1927

radeon_get_ib_value(p, idx+1) +

sys/dev/drm/radeon/evergreen_cs.c

1928

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2100

(radeon_get_ib_value(p, idx+1) & 0xfffffffc) +

sys/dev/drm/radeon/evergreen_cs.c

2101

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2118

command = radeon_get_ib_value(p, idx+4);

sys/dev/drm/radeon/evergreen_cs.c

2120

info = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

2153

tmp = radeon_get_ib_value(p, idx) +

sys/dev/drm/radeon/evergreen_cs.c

2154

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2191

tmp = radeon_get_ib_value(p, idx+2) +

sys/dev/drm/radeon/evergreen_cs.c

2192

((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2223

if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||

sys/dev/drm/radeon/evergreen_cs.c

2224

radeon_get_ib_value(p, idx + 2) != 0) {

sys/dev/drm/radeon/evergreen_cs.c

2247

(radeon_get_ib_value(p, idx+1) & 0xfffffff8) +

sys/dev/drm/radeon/evergreen_cs.c

2248

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2269

(radeon_get_ib_value(p, idx+1) & 0xfffffffc) +

sys/dev/drm/radeon/evergreen_cs.c

2270

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2291

(radeon_get_ib_value(p, idx+1) & 0xfffffffc) +

sys/dev/drm/radeon/evergreen_cs.c

2292

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/evergreen_cs.c

2350

switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {

sys/dev/drm/radeon/evergreen_cs.c

2414

offset = radeon_get_ib_value(p, idx+1+(i*8)+0);

sys/dev/drm/radeon/evergreen_cs.c

2415

size = radeon_get_ib_value(p, idx+1+(i*8)+1);

sys/dev/drm/radeon/evergreen_cs.c

2496

offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

2497

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2515

offset = radeon_get_ib_value(p, idx+3);

sys/dev/drm/radeon/evergreen_cs.c

2516

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2540

offset = radeon_get_ib_value(p, idx+0);

sys/dev/drm/radeon/evergreen_cs.c

2541

offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;

sys/dev/drm/radeon/evergreen_cs.c

2569

offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

2570

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2581

reg = radeon_get_ib_value(p, idx+1) << 2;

sys/dev/drm/radeon/evergreen_cs.c

2596

offset = radeon_get_ib_value(p, idx+3);

sys/dev/drm/radeon/evergreen_cs.c

2597

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2608

reg = radeon_get_ib_value(p, idx+3) << 2;

sys/dev/drm/radeon/evergreen_cs.c

2646

offset = radeon_get_ib_value(p, idx + 1);

sys/dev/drm/radeon/evergreen_cs.c

2650

offset += ((u64)(radeon_get_ib_value(p, idx + 2) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2812

header = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/evergreen_cs.c

2827

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

2835

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

2836

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2867

src_offset = radeon_get_ib_value(p, idx+2);

sys/dev/drm/radeon/evergreen_cs.c

2868

src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2869

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

2870

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2890

if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {

sys/dev/drm/radeon/evergreen_cs.c

2892

src_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

2896

dst_offset = radeon_get_ib_value(p, idx + 7);

sys/dev/drm/radeon/evergreen_cs.c

2897

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2902

src_offset = radeon_get_ib_value(p, idx+7);

sys/dev/drm/radeon/evergreen_cs.c

2903

src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2907

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

2926

src_offset = radeon_get_ib_value(p, idx+2);

sys/dev/drm/radeon/evergreen_cs.c

2927

src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2928

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

2929

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2968

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

2969

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2970

dst2_offset = radeon_get_ib_value(p, idx+2);

sys/dev/drm/radeon/evergreen_cs.c

2971

dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2972

src_offset = radeon_get_ib_value(p, idx+3);

sys/dev/drm/radeon/evergreen_cs.c

2973

src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

2999

if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {

sys/dev/drm/radeon/evergreen_cs.c

3008

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

3010

dst2_offset = radeon_get_ib_value(p, idx+2);

sys/dev/drm/radeon/evergreen_cs.c

3012

src_offset = radeon_get_ib_value(p, idx+8);

sys/dev/drm/radeon/evergreen_cs.c

3013

src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

3043

if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {

sys/dev/drm/radeon/evergreen_cs.c

3061

if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {

sys/dev/drm/radeon/evergreen_cs.c

3070

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

3072

dst2_offset = radeon_get_ib_value(p, idx+2);

sys/dev/drm/radeon/evergreen_cs.c

3074

src_offset = radeon_get_ib_value(p, idx+8);

sys/dev/drm/radeon/evergreen_cs.c

3075

src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

3101

if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {

sys/dev/drm/radeon/evergreen_cs.c

3103

src_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

3107

dst_offset = radeon_get_ib_value(p, idx+7);

sys/dev/drm/radeon/evergreen_cs.c

3108

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

3113

src_offset = radeon_get_ib_value(p, idx+7);

sys/dev/drm/radeon/evergreen_cs.c

3114

src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

3118

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

3148

if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) {

sys/dev/drm/radeon/evergreen_cs.c

3157

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

3159

dst2_offset = radeon_get_ib_value(p, idx+2);

sys/dev/drm/radeon/evergreen_cs.c

3161

src_offset = radeon_get_ib_value(p, idx+8);

sys/dev/drm/radeon/evergreen_cs.c

3162

src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;

sys/dev/drm/radeon/evergreen_cs.c

3195

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/evergreen_cs.c

3196

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;

sys/dev/drm/radeon/evergreen_cs.c

762

texdw[0] = radeon_get_ib_value(p, idx + 0);

sys/dev/drm/radeon/evergreen_cs.c

763

texdw[1] = radeon_get_ib_value(p, idx + 1);

sys/dev/drm/radeon/evergreen_cs.c

764

texdw[2] = radeon_get_ib_value(p, idx + 2);

sys/dev/drm/radeon/evergreen_cs.c

765

texdw[3] = radeon_get_ib_value(p, idx + 3);

sys/dev/drm/radeon/evergreen_cs.c

766

texdw[4] = radeon_get_ib_value(p, idx + 4);

sys/dev/drm/radeon/evergreen_cs.c

767

texdw[5] = radeon_get_ib_value(p, idx + 5);

sys/dev/drm/radeon/evergreen_cs.c

768

texdw[6] = radeon_get_ib_value(p, idx + 6);

sys/dev/drm/radeon/evergreen_cs.c

769

texdw[7] = radeon_get_ib_value(p, idx + 7);

sys/dev/drm/radeon/r100.c

1288

value = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r100.c

1324

c = radeon_get_ib_value(p, idx++) & 0x1F;

sys/dev/drm/radeon/r100.c

1340

idx_value = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r100.c

1341

ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1353

ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1366

idx_value = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r100.c

1367

ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1458

if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {

sys/dev/drm/radeon/r100.c

1472

header = radeon_get_ib_value(p, h_idx);

sys/dev/drm/radeon/r100.c

1473

crtc_id = radeon_get_ib_value(p, h_idx + 5);

sys/dev/drm/radeon/r100.c

1577

idx_value = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r100.c

1909

value = radeon_get_ib_value(p, idx + 2);

sys/dev/drm/radeon/r100.c

1945

ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1959

ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r100.c

1961

track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));

sys/dev/drm/radeon/r100.c

1966

track->max_indx = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/r100.c

1968

track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);

sys/dev/drm/radeon/r100.c

1975

if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {

sys/dev/drm/radeon/r100.c

1979

track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));

sys/dev/drm/radeon/r100.c

1980

track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);

sys/dev/drm/radeon/r100.c

1988

if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {

sys/dev/drm/radeon/r100.c

1992

track->vap_vf_cntl = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r100.c

2000

track->vap_vf_cntl = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r100.c

2007

track->vap_vf_cntl = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r100.c

2014

track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);

sys/dev/drm/radeon/r100.c

2021

track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);

sys/dev/drm/radeon/r200.c

161

idx_value = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r300.c

1191

ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);

sys/dev/drm/radeon/r300.c

1202

if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {

sys/dev/drm/radeon/r300.c

1206

track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);

sys/dev/drm/radeon/r300.c

1217

if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {

sys/dev/drm/radeon/r300.c

1221

track->vap_vf_cntl = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r300.c

1229

track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);

sys/dev/drm/radeon/r300.c

1236

track->vap_vf_cntl = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r300.c

1243

track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);

sys/dev/drm/radeon/r300.c

1250

track->vap_vf_cntl = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r300.c

635

idx_value = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1026

track->sq_config = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1029

track->db_depth_control = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1041

track->db_depth_info = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1052

track->db_depth_info = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1057

track->db_depth_view = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1061

track->db_depth_size = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1066

track->vgt_strmout_en = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1070

track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1084

track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;

sys/dev/drm/radeon/r600_cs.c

1096

track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;

sys/dev/drm/radeon/r600_cs.c

1109

track->cb_target_mask = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1113

track->cb_shader_mask = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1116

tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));

sys/dev/drm/radeon/r600_cs.c

1122

tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));

sys/dev/drm/radeon/r600_cs.c

1142

track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1152

track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1165

track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1177

track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1261

track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1281

track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;

sys/dev/drm/radeon/r600_cs.c

1295

track->db_offset = radeon_get_ib_value(p, idx) << 8;

sys/dev/drm/radeon/r600_cs.c

1308

track->htile_offset = radeon_get_ib_value(p, idx) << 8;

sys/dev/drm/radeon/r600_cs.c

1314

track->htile_surface = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1390

track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;

sys/dev/drm/radeon/r600_cs.c

1494

word0 = radeon_get_ib_value(p, idx + 0);

sys/dev/drm/radeon/r600_cs.c

1501

word1 = radeon_get_ib_value(p, idx + 1);

sys/dev/drm/radeon/r600_cs.c

1502

word2 = radeon_get_ib_value(p, idx + 2) << 8;

sys/dev/drm/radeon/r600_cs.c

1503

word3 = radeon_get_ib_value(p, idx + 3) << 8;

sys/dev/drm/radeon/r600_cs.c

1504

word4 = radeon_get_ib_value(p, idx + 4);

sys/dev/drm/radeon/r600_cs.c

1505

word5 = radeon_get_ib_value(p, idx + 5);

sys/dev/drm/radeon/r600_cs.c

1641

idx_value = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

1655

tmp = radeon_get_ib_value(p, idx + 1);

sys/dev/drm/radeon/r600_cs.c

1716

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/drm/radeon/r600_cs.c

1767

(radeon_get_ib_value(p, idx+1) & 0xfffffff0) +

sys/dev/drm/radeon/r600_cs.c

1768

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/r600_cs.c

1785

command = radeon_get_ib_value(p, idx+4);

sys/dev/drm/radeon/r600_cs.c

1803

tmp = radeon_get_ib_value(p, idx) +

sys/dev/drm/radeon/r600_cs.c

1804

((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);

sys/dev/drm/radeon/r600_cs.c

1833

tmp = radeon_get_ib_value(p, idx+2) +

sys/dev/drm/radeon/r600_cs.c

1834

((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);

sys/dev/drm/radeon/r600_cs.c

1855

if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||

sys/dev/drm/radeon/r600_cs.c

1856

radeon_get_ib_value(p, idx + 2) != 0) {

sys/dev/drm/radeon/r600_cs.c

1879

(radeon_get_ib_value(p, idx+1) & 0xfffffff8) +

sys/dev/drm/radeon/r600_cs.c

1880

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/r600_cs.c

1901

(radeon_get_ib_value(p, idx+1) & 0xfffffffc) +

sys/dev/drm/radeon/r600_cs.c

1902

((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);

sys/dev/drm/radeon/r600_cs.c

1957

switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {

sys/dev/drm/radeon/r600_cs.c

1983

base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),

sys/dev/drm/radeon/r600_cs.c

1984

mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),

sys/dev/drm/radeon/r600_cs.c

2000

offset = radeon_get_ib_value(p, idx+1+(i*7)+0);

sys/dev/drm/radeon/r600_cs.c

2001

size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;

sys/dev/drm/radeon/r600_cs.c

2107

offset = radeon_get_ib_value(p, idx+1) << 8;

sys/dev/drm/radeon/r600_cs.c

2145

offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/r600_cs.c

2146

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2164

offset = radeon_get_ib_value(p, idx+3);

sys/dev/drm/radeon/r600_cs.c

2165

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2189

offset = radeon_get_ib_value(p, idx+0);

sys/dev/drm/radeon/r600_cs.c

2190

offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;

sys/dev/drm/radeon/r600_cs.c

2218

offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/r600_cs.c

2219

offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2230

reg = radeon_get_ib_value(p, idx+1) << 2;

sys/dev/drm/radeon/r600_cs.c

2242

offset = radeon_get_ib_value(p, idx+3);

sys/dev/drm/radeon/r600_cs.c

2243

offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2254

reg = radeon_get_ib_value(p, idx+3) << 2;

sys/dev/drm/radeon/r600_cs.c

2395

header = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/r600_cs.c

2408

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/r600_cs.c

2414

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/r600_cs.c

2415

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2439

idx_value = radeon_get_ib_value(p, idx + 2);

sys/dev/drm/radeon/r600_cs.c

2443

src_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/r600_cs.c

2447

dst_offset = radeon_get_ib_value(p, idx+5);

sys/dev/drm/radeon/r600_cs.c

2448

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2453

src_offset = radeon_get_ib_value(p, idx+5);

sys/dev/drm/radeon/r600_cs.c

2454

src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2458

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/r600_cs.c

2465

src_offset = radeon_get_ib_value(p, idx+2);

sys/dev/drm/radeon/r600_cs.c

2466

src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2467

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/r600_cs.c

2468

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2476

src_offset = radeon_get_ib_value(p, idx+2);

sys/dev/drm/radeon/r600_cs.c

2477

src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;

sys/dev/drm/radeon/r600_cs.c

2478

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/r600_cs.c

2479

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;

sys/dev/drm/radeon/r600_cs.c

2509

dst_offset = radeon_get_ib_value(p, idx+1);

sys/dev/drm/radeon/r600_cs.c

2510

dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;

sys/dev/drm/radeon/r600_cs.c

851

wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);

sys/dev/drm/radeon/r600_cs.c

867

if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) {

sys/dev/drm/radeon/r600_cs.c

872

if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) {

sys/dev/drm/radeon/r600_cs.c

886

header = radeon_get_ib_value(p, h_idx);

sys/dev/drm/radeon/r600_cs.c

887

crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);

sys/dev/drm/radeon/radeon_cs.c

743

header = radeon_get_ib_value(p, idx);

sys/dev/drm/radeon/radeon_cs.c

779

printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));

sys/dev/drm/radeon/radeon_cs.c

781

printk("\t0x%08x\n", radeon_get_ib_value(p, i));

sys/dev/drm/radeon/radeon_cs.c

864

idx = radeon_get_ib_value(p, p3reloc.idx + 1);

sys/dev/drm/radeon/radeon_uvd.c

583

offset = radeon_get_ib_value(p, data0);

sys/dev/drm/radeon/radeon_uvd.c

584

idx = radeon_get_ib_value(p, data1);

sys/dev/drm/radeon/radeon_uvd.c

599

cmd = radeon_get_ib_value(p, p->idx) >> 1;

sys/dev/drm/radeon/radeon_vce.c

479

offset = radeon_get_ib_value(p, lo);

sys/dev/drm/radeon/radeon_vce.c

480

idx = radeon_get_ib_value(p, hi);

sys/dev/drm/radeon/radeon_vce.c

566

uint32_t len = radeon_get_ib_value(p, p->idx);

sys/dev/drm/radeon/radeon_vce.c

567

uint32_t cmd = radeon_get_ib_value(p, p->idx + 1);

sys/dev/drm/radeon/radeon_vce.c

583

handle = radeon_get_ib_value(p, p->idx + 2);

sys/dev/drm/radeon/radeon_vce.c

602

*size = radeon_get_ib_value(p, p->idx + 8) *

sys/dev/drm/radeon/radeon_vce.c

603

radeon_get_ib_value(p, p->idx + 10) *

sys/dev/drm/radeon/radeon_vce.c

639

tmp = radeon_get_ib_value(p, p->idx + 4);