sys/dev/drm/radeon/atombios_crtc.c

1001

radeon_crtc->ss_enabled =

sys/dev/drm/radeon/atombios_crtc.c

1003

&radeon_crtc->ss,

sys/dev/drm/radeon/atombios_crtc.c

1005

if (!radeon_crtc->ss_enabled)

sys/dev/drm/radeon/atombios_crtc.c

1006

radeon_crtc->ss_enabled =

sys/dev/drm/radeon/atombios_crtc.c

1008

&radeon_crtc->ss,

sys/dev/drm/radeon/atombios_crtc.c

1011

radeon_crtc->ss_enabled =

sys/dev/drm/radeon/atombios_crtc.c

1013

&radeon_crtc->ss,

sys/dev/drm/radeon/atombios_crtc.c

1017

radeon_crtc->ss_enabled = false;

sys/dev/drm/radeon/atombios_crtc.c

1022

radeon_crtc->ss_enabled =

sys/dev/drm/radeon/atombios_crtc.c

1024

&radeon_crtc->ss,

sys/dev/drm/radeon/atombios_crtc.c

1028

radeon_crtc->ss_enabled =

sys/dev/drm/radeon/atombios_crtc.c

1030

&radeon_crtc->ss,

sys/dev/drm/radeon/atombios_crtc.c

1035

radeon_crtc->ss_enabled =

sys/dev/drm/radeon/atombios_crtc.c

1037

&radeon_crtc->ss,

sys/dev/drm/radeon/atombios_crtc.c

104

args.ucScaler = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_crtc.c

1043

radeon_crtc->ss_enabled =

sys/dev/drm/radeon/atombios_crtc.c

1045

&radeon_crtc->ss,

sys/dev/drm/radeon/atombios_crtc.c

1055

radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);

sys/dev/drm/radeon/atombios_crtc.c

1062

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

1066

to_radeon_encoder(radeon_crtc->encoder);

sys/dev/drm/radeon/atombios_crtc.c

1071

int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);

sys/dev/drm/radeon/atombios_crtc.c

1076

(radeon_crtc->bpc > 8))

sys/dev/drm/radeon/atombios_crtc.c

1077

clock = radeon_crtc->adjusted_clock;

sys/dev/drm/radeon/atombios_crtc.c

1079

switch (radeon_crtc->pll_id) {

sys/dev/drm/radeon/atombios_crtc.c

1094

pll->flags = radeon_crtc->pll_flags;

sys/dev/drm/radeon/atombios_crtc.c

1095

pll->reference_div = radeon_crtc->pll_reference_div;

sys/dev/drm/radeon/atombios_crtc.c

1096

pll->post_div = radeon_crtc->pll_post_div;

sys/dev/drm/radeon/atombios_crtc.c

1100

radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,

sys/dev/drm/radeon/atombios_crtc.c

1103

radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,

sys/dev/drm/radeon/atombios_crtc.c

1106

radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,

sys/dev/drm/radeon/atombios_crtc.c

1109

atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,

sys/dev/drm/radeon/atombios_crtc.c

1110

radeon_crtc->crtc_id, &radeon_crtc->ss);

sys/dev/drm/radeon/atombios_crtc.c

1112

atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,

sys/dev/drm/radeon/atombios_crtc.c

1115

radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);

sys/dev/drm/radeon/atombios_crtc.c

1117

if (radeon_crtc->ss_enabled) {

sys/dev/drm/radeon/atombios_crtc.c

1122

(u32)radeon_crtc->ss.percentage) /

sys/dev/drm/radeon/atombios_crtc.c

1123

(100 * (u32)radeon_crtc->ss.percentage_divider);

sys/dev/drm/radeon/atombios_crtc.c

1124

radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;

sys/dev/drm/radeon/atombios_crtc.c

1125

radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &

sys/dev/drm/radeon/atombios_crtc.c

1127

if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)

sys/dev/drm/radeon/atombios_crtc.c

1128

step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /

sys/dev/drm/radeon/atombios_crtc.c

1131

step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /

sys/dev/drm/radeon/atombios_crtc.c

1133

radeon_crtc->ss.step = step_size;

sys/dev/drm/radeon/atombios_crtc.c

1136

atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,

sys/dev/drm/radeon/atombios_crtc.c

1137

radeon_crtc->crtc_id, &radeon_crtc->ss);

sys/dev/drm/radeon/atombios_crtc.c

1145

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

1355

switch (radeon_crtc->crtc_id) {

sys/dev/drm/radeon/atombios_crtc.c

1381

WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1383

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1385

WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1387

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1389

WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

139

switch (radeon_crtc->rmx_type) {

sys/dev/drm/radeon/atombios_crtc.c

1391

WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);

sys/dev/drm/radeon/atombios_crtc.c

1392

WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);

sys/dev/drm/radeon/atombios_crtc.c

1399

WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1406

WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1407

WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1408

WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1409

WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1410

WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);

sys/dev/drm/radeon/atombios_crtc.c

1411

WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);

sys/dev/drm/radeon/atombios_crtc.c

1414

WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);

sys/dev/drm/radeon/atombios_crtc.c

1415

WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);

sys/dev/drm/radeon/atombios_crtc.c

1418

WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1421

WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1425

WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1432

WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1436

WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1457

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

1573

if (radeon_crtc->crtc_id == 0)

sys/dev/drm/radeon/atombios_crtc.c

1581

WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1584

if (radeon_crtc->crtc_id) {

sys/dev/drm/radeon/atombios_crtc.c

1592

WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1595

radeon_crtc->crtc_offset, (u32) fb_location);

sys/dev/drm/radeon/atombios_crtc.c

1596

WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);

sys/dev/drm/radeon/atombios_crtc.c

1598

WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);

sys/dev/drm/radeon/atombios_crtc.c

160

atom_rv515_force_tv_scaler(rdev, radeon_crtc);

sys/dev/drm/radeon/atombios_crtc.c

1601

WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1607

WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1608

WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1609

WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1610

WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1611

WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);

sys/dev/drm/radeon/atombios_crtc.c

1612

WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);

sys/dev/drm/radeon/atombios_crtc.c

1615

WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);

sys/dev/drm/radeon/atombios_crtc.c

1616

WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);

sys/dev/drm/radeon/atombios_crtc.c

1618

WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1622

WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1626

WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1630

WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);

sys/dev/drm/radeon/atombios_crtc.c

166

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

1681

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

1684

switch (radeon_crtc->crtc_id) {

sys/dev/drm/radeon/atombios_crtc.c

1711

struct radeon_crtc *test_radeon_crtc;

sys/dev/drm/radeon/atombios_crtc.c

1739

struct radeon_crtc *test_radeon_crtc;

sys/dev/drm/radeon/atombios_crtc.c

175

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_crtc.c

1770

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

1774

struct radeon_crtc *test_radeon_crtc;

sys/dev/drm/radeon/atombios_crtc.c

1777

adjusted_clock = radeon_crtc->adjusted_clock;

sys/dev/drm/radeon/atombios_crtc.c

1793

if (test_radeon_crtc->connector == radeon_crtc->connector) {

sys/dev/drm/radeon/atombios_crtc.c

1802

(radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&

sys/dev/drm/radeon/atombios_crtc.c

183

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

1849

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

1853

to_radeon_encoder(radeon_crtc->encoder);

sys/dev/drm/radeon/atombios_crtc.c

1858

if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

sys/dev/drm/radeon/atombios_crtc.c

1905

else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

sys/dev/drm/radeon/atombios_crtc.c

191

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_crtc.c

1932

if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

sys/dev/drm/radeon/atombios_crtc.c

1955

if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

sys/dev/drm/radeon/atombios_crtc.c

199

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

2001

return radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_crtc.c

2030

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

2034

to_radeon_encoder(radeon_crtc->encoder);

sys/dev/drm/radeon/atombios_crtc.c

2041

if (!radeon_crtc->adjusted_clock)

sys/dev/drm/radeon/atombios_crtc.c

2055

if (radeon_crtc->crtc_id == 0)

sys/dev/drm/radeon/atombios_crtc.c

2064

radeon_crtc->hw_mode = *adjusted_mode;

sys/dev/drm/radeon/atombios_crtc.c

207

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_crtc.c

2073

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

2080

radeon_crtc->encoder = encoder;

sys/dev/drm/radeon/atombios_crtc.c

2081

radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);

sys/dev/drm/radeon/atombios_crtc.c

2085

if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {

sys/dev/drm/radeon/atombios_crtc.c

2086

radeon_crtc->encoder = NULL;

sys/dev/drm/radeon/atombios_crtc.c

2087

radeon_crtc->connector = NULL;

sys/dev/drm/radeon/atombios_crtc.c

2090

if (radeon_crtc->encoder) {

sys/dev/drm/radeon/atombios_crtc.c

2092

to_radeon_encoder(radeon_crtc->encoder);

sys/dev/drm/radeon/atombios_crtc.c

2094

radeon_crtc->output_csc = radeon_encoder->output_csc;

sys/dev/drm/radeon/atombios_crtc.c

2101

radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);

sys/dev/drm/radeon/atombios_crtc.c

2103

if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&

sys/dev/drm/radeon/atombios_crtc.c

2104

!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))

sys/dev/drm/radeon/atombios_crtc.c

2131

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

2153

WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

2155

WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

2163

i != radeon_crtc->crtc_id &&

sys/dev/drm/radeon/atombios_crtc.c

2164

radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {

sys/dev/drm/radeon/atombios_crtc.c

2172

switch (radeon_crtc->pll_id) {

sys/dev/drm/radeon/atombios_crtc.c

2176

atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,

sys/dev/drm/radeon/atombios_crtc.c

2185

atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,

sys/dev/drm/radeon/atombios_crtc.c

2192

radeon_crtc->pll_id = ATOM_PPLL_INVALID;

sys/dev/drm/radeon/atombios_crtc.c

2193

radeon_crtc->adjusted_clock = 0;

sys/dev/drm/radeon/atombios_crtc.c

2194

radeon_crtc->encoder = NULL;

sys/dev/drm/radeon/atombios_crtc.c

2195

radeon_crtc->connector = NULL;

sys/dev/drm/radeon/atombios_crtc.c

2210

struct radeon_crtc *radeon_crtc)

sys/dev/drm/radeon/atombios_crtc.c

2215

switch (radeon_crtc->crtc_id) {

sys/dev/drm/radeon/atombios_crtc.c

2218

radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;

sys/dev/drm/radeon/atombios_crtc.c

2221

radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;

sys/dev/drm/radeon/atombios_crtc.c

2224

radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;

sys/dev/drm/radeon/atombios_crtc.c

2227

radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;

sys/dev/drm/radeon/atombios_crtc.c

2230

radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;

sys/dev/drm/radeon/atombios_crtc.c

2233

radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;

sys/dev/drm/radeon/atombios_crtc.c

2237

if (radeon_crtc->crtc_id == 1)

sys/dev/drm/radeon/atombios_crtc.c

2238

radeon_crtc->crtc_offset =

sys/dev/drm/radeon/atombios_crtc.c

2241

radeon_crtc->crtc_offset = 0;

sys/dev/drm/radeon/atombios_crtc.c

2243

radeon_crtc->pll_id = ATOM_PPLL_INVALID;

sys/dev/drm/radeon/atombios_crtc.c

2244

radeon_crtc->adjusted_clock = 0;

sys/dev/drm/radeon/atombios_crtc.c

2245

radeon_crtc->encoder = NULL;

sys/dev/drm/radeon/atombios_crtc.c

2246

radeon_crtc->connector = NULL;

sys/dev/drm/radeon/atombios_crtc.c

2247

drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);

sys/dev/drm/radeon/atombios_crtc.c

225

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

235

vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);

sys/dev/drm/radeon/atombios_crtc.c

236

WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);

sys/dev/drm/radeon/atombios_crtc.c

239

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_crtc.c

245

WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);

sys/dev/drm/radeon/atombios_crtc.c

251

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

259

args.ucDispPipeId = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_crtc.c

269

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

273

radeon_crtc->enabled = true;

sys/dev/drm/radeon/atombios_crtc.c

278

if (dev->num_crtcs > radeon_crtc->crtc_id)

sys/dev/drm/radeon/atombios_crtc.c

285

if (dev->num_crtcs > radeon_crtc->crtc_id)

sys/dev/drm/radeon/atombios_crtc.c

287

if (radeon_crtc->enabled)

sys/dev/drm/radeon/atombios_crtc.c

292

radeon_crtc->enabled = false;

sys/dev/drm/radeon/atombios_crtc.c

303

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

311

args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));

sys/dev/drm/radeon/atombios_crtc.c

313

cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));

sys/dev/drm/radeon/atombios_crtc.c

314

args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));

sys/dev/drm/radeon/atombios_crtc.c

316

cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));

sys/dev/drm/radeon/atombios_crtc.c

318

cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);

sys/dev/drm/radeon/atombios_crtc.c

322

cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);

sys/dev/drm/radeon/atombios_crtc.c

325

args.ucH_Border = radeon_crtc->h_border;

sys/dev/drm/radeon/atombios_crtc.c

326

args.ucV_Border = radeon_crtc->v_border;

sys/dev/drm/radeon/atombios_crtc.c

342

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_crtc.c

350

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

369

args.ucOverscanRight = radeon_crtc->h_border;

sys/dev/drm/radeon/atombios_crtc.c

370

args.ucOverscanLeft = radeon_crtc->h_border;

sys/dev/drm/radeon/atombios_crtc.c

371

args.ucOverscanBottom = radeon_crtc->v_border;

sys/dev/drm/radeon/atombios_crtc.c

372

args.ucOverscanTop = radeon_crtc->v_border;

sys/dev/drm/radeon/atombios_crtc.c

388

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_crtc.c

41

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

48

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_crtc.c

50

switch (radeon_crtc->rmx_type) {

sys/dev/drm/radeon/atombios_crtc.c

558

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

561

struct drm_encoder *encoder = radeon_crtc->encoder;

sys/dev/drm/radeon/atombios_crtc.c

568

int bpc = radeon_crtc->bpc;

sys/dev/drm/radeon/atombios_crtc.c

572

radeon_crtc->pll_flags = 0;

sys/dev/drm/radeon/atombios_crtc.c

578

radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/

sys/dev/drm/radeon/atombios_crtc.c

582

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;

sys/dev/drm/radeon/atombios_crtc.c

584

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;

sys/dev/drm/radeon/atombios_crtc.c

587

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;

sys/dev/drm/radeon/atombios_crtc.c

590

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

sys/dev/drm/radeon/atombios_crtc.c

593

&& !radeon_crtc->ss_enabled)

sys/dev/drm/radeon/atombios_crtc.c

594

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

sys/dev/drm/radeon/atombios_crtc.c

596

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

sys/dev/drm/radeon/atombios_crtc.c

598

radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;

sys/dev/drm/radeon/atombios_crtc.c

601

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;

sys/dev/drm/radeon/atombios_crtc.c

603

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;

sys/dev/drm/radeon/atombios_crtc.c

626

if (radeon_crtc->ss_enabled) {

sys/dev/drm/radeon/atombios_crtc.c

627

if (radeon_crtc->ss.refdiv) {

sys/dev/drm/radeon/atombios_crtc.c

628

radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;

sys/dev/drm/radeon/atombios_crtc.c

629

radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;

sys/dev/drm/radeon/atombios_crtc.c

633

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

sys/dev/drm/radeon/atombios_crtc.c

643

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;

sys/dev/drm/radeon/atombios_crtc.c

645

radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;

sys/dev/drm/radeon/atombios_crtc.c

648

radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;

sys/dev/drm/radeon/atombios_crtc.c

650

radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;

sys/dev/drm/radeon/atombios_crtc.c

695

if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)

sys/dev/drm/radeon/atombios_crtc.c

708

if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)

sys/dev/drm/radeon/atombios_crtc.c

71

args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);

sys/dev/drm/radeon/atombios_crtc.c

72

args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);

sys/dev/drm/radeon/atombios_crtc.c

73

args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);

sys/dev/drm/radeon/atombios_crtc.c

736

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

sys/dev/drm/radeon/atombios_crtc.c

737

radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;

sys/dev/drm/radeon/atombios_crtc.c

738

radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;

sys/dev/drm/radeon/atombios_crtc.c

74

args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);

sys/dev/drm/radeon/atombios_crtc.c

741

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

sys/dev/drm/radeon/atombios_crtc.c

742

radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;

sys/dev/drm/radeon/atombios_crtc.c

743

radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;

sys/dev/drm/radeon/atombios_crtc.c

84

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

88

to_radeon_encoder(radeon_crtc->encoder);

sys/dev/drm/radeon/atombios_crtc.c

93

if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)

sys/dev/drm/radeon/atombios_crtc.c

962

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/atombios_crtc.c

966

to_radeon_encoder(radeon_crtc->encoder);

sys/dev/drm/radeon/atombios_crtc.c

967

int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);

sys/dev/drm/radeon/atombios_crtc.c

969

radeon_crtc->bpc = 8;

sys/dev/drm/radeon/atombios_crtc.c

970

radeon_crtc->ss_enabled = false;

sys/dev/drm/radeon/atombios_crtc.c

975

(radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {

sys/dev/drm/radeon/atombios_crtc.c

978

radeon_get_connector_for_encoder(radeon_crtc->encoder);

sys/dev/drm/radeon/atombios_crtc.c

987

radeon_crtc->bpc = radeon_get_monitor_bpc(connector);

sys/dev/drm/radeon/atombios_crtc.c

995

radeon_crtc->ss_enabled =

sys/dev/drm/radeon/atombios_crtc.c

996

radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,

sys/dev/drm/radeon/atombios_encoders.c

1111

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/atombios_encoders.c

1112

pll_id = radeon_crtc->pll_id;

sys/dev/drm/radeon/atombios_encoders.c

1599

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/atombios_encoders.c

1615

(radeon_crtc->crtc_id << 18)));

sys/dev/drm/radeon/atombios_encoders.c

1617

WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));

sys/dev/drm/radeon/atombios_encoders.c

1623

args.ucCRTC = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_encoders.c

1922

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/atombios_encoders.c

1939

args.v1.ucCRTC = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_encoders.c

1942

args.v1.ucCRTC = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_encoders.c

1944

args.v1.ucCRTC = radeon_crtc->crtc_id << 2;

sys/dev/drm/radeon/atombios_encoders.c

1985

args.v2.ucCRTC = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_encoders.c

2062

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/drm/radeon/atombios_encoders.c

2070

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/atombios_encoders.c

2083

args.v2.ucCRTC = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_encoders.c

2119

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/atombios_encoders.c

2140

WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_encoders.c

2143

WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_encoders.c

2146

WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_encoders.c

2149

WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_encoders.c

2152

WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_encoders.c

2155

WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_encoders.c

2171

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/atombios_encoders.c

2219

enc_idx = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_encoders.c

2254

enc_idx = radeon_crtc->crtc_id;

sys/dev/drm/radeon/atombios_encoders.c

517

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/atombios_encoders.c

518

bpc = radeon_crtc->bpc;

sys/dev/drm/radeon/cik.c

8762

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/cik.c

8818

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/cik.c

8835

struct radeon_crtc *radeon_crtc,

sys/dev/drm/radeon/cik.c

8839

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

sys/dev/drm/radeon/cik.c

8848

if (radeon_crtc->base.enabled && mode) {

sys/dev/drm/radeon/cik.c

8868

WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/cik.c

8880

if (radeon_crtc->base.enabled && mode) {

sys/dev/drm/radeon/cik.c

9264

struct radeon_crtc *radeon_crtc,

sys/dev/drm/radeon/cik.c

9267

struct drm_display_mode *mode = &radeon_crtc->base.mode;

sys/dev/drm/radeon/cik.c

9274

if (radeon_crtc->base.enabled && num_heads && mode) {

sys/dev/drm/radeon/cik.c

9300

wm_high.vsc = radeon_crtc->vsc;

sys/dev/drm/radeon/cik.c

9302

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/drm/radeon/cik.c

9340

wm_low.vsc = radeon_crtc->vsc;

sys/dev/drm/radeon/cik.c

9342

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/drm/radeon/cik.c

9362

radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

sys/dev/drm/radeon/cik.c

9366

wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/cik.c

9370

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/cik.c

9371

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/cik.c

9375

tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/cik.c

9378

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/cik.c

9379

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/cik.c

9383

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);

sys/dev/drm/radeon/cik.c

9386

radeon_crtc->line_time = line_time;

sys/dev/drm/radeon/cik.c

9387

radeon_crtc->wm_high = latency_watermark_a;

sys/dev/drm/radeon/cik.c

9388

radeon_crtc->wm_low = latency_watermark_b;

sys/dev/drm/radeon/dce3_1_afmt.c

123

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/dce3_1_afmt.c

125

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/drm/radeon/dce6_afmt.c

282

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/dce6_afmt.c

284

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/drm/radeon/dce6_afmt.c

303

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/dce6_afmt.c

305

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/drm/radeon/evergreen.c

1282

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/evergreen.c

1330

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/evergreen.c

1403

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/drm/radeon/evergreen.c

1406

WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/evergreen.c

1408

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/evergreen.c

1410

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/evergreen.c

1413

RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/evergreen.c

1426

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/drm/radeon/evergreen.c

1429

return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &

sys/dev/drm/radeon/evergreen.c

1657

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/evergreen.c

1662

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/evergreen.c

1663

if (radeon_crtc->enabled) {

sys/dev/drm/radeon/evergreen.c

1664

tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/evergreen.c

1666

WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/evergreen.c

1682

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/evergreen.c

1687

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/evergreen.c

1688

if (radeon_crtc->enabled) {

sys/dev/drm/radeon/evergreen.c

1689

tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/evergreen.c

1691

WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/evergreen.c

1806

struct radeon_crtc *radeon_crtc,

sys/dev/drm/radeon/evergreen.c

1811

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

sys/dev/drm/radeon/evergreen.c

1833

if (radeon_crtc->base.enabled && mode) {

sys/dev/drm/radeon/evergreen.c

1847

if (radeon_crtc->crtc_id % 2)

sys/dev/drm/radeon/evergreen.c

1849

WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/evergreen.c

1862

if (radeon_crtc->base.enabled && mode) {

sys/dev/drm/radeon/evergreen.c

2135

struct radeon_crtc *radeon_crtc,

sys/dev/drm/radeon/evergreen.c

2138

struct drm_display_mode *mode = &radeon_crtc->base.mode;

sys/dev/drm/radeon/evergreen.c

2147

u32 pipe_offset = radeon_crtc->crtc_id * 16;

sys/dev/drm/radeon/evergreen.c

2151

if (radeon_crtc->base.enabled && num_heads && mode) {

sys/dev/drm/radeon/evergreen.c

2179

wm_high.vsc = radeon_crtc->vsc;

sys/dev/drm/radeon/evergreen.c

2181

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/drm/radeon/evergreen.c

2206

wm_low.vsc = radeon_crtc->vsc;

sys/dev/drm/radeon/evergreen.c

2208

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/drm/radeon/evergreen.c

2242

c.full = dfixed_mul(c, radeon_crtc->hsc);

sys/dev/drm/radeon/evergreen.c

2254

c.full = dfixed_mul(c, radeon_crtc->hsc);

sys/dev/drm/radeon/evergreen.c

2262

radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

sys/dev/drm/radeon/evergreen.c

2286

WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);

sys/dev/drm/radeon/evergreen.c

2287

WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);

sys/dev/drm/radeon/evergreen.c

2290

radeon_crtc->line_time = line_time;

sys/dev/drm/radeon/evergreen.c

2291

radeon_crtc->wm_high = latency_watermark_a;

sys/dev/drm/radeon/evergreen.c

2292

radeon_crtc->wm_low = latency_watermark_b;

sys/dev/drm/radeon/evergreen_hdmi.c

243

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/evergreen_hdmi.c

245

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/drm/radeon/evergreen_hdmi.c

288

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/evergreen_hdmi.c

290

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/drm/radeon/evergreen_hdmi.c

80

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/evergreen_hdmi.c

81

bpc = radeon_crtc->bpc;

sys/dev/drm/radeon/r100.c

1437

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/r100.c

1480

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/r100.c

1481

crtc_id = radeon_crtc->crtc_id;

sys/dev/drm/radeon/r100.c

158

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/drm/radeon/r100.c

164

WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/r100.c

168

if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)

sys/dev/drm/radeon/r100.c

176

WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/r100.c

191

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/drm/radeon/r100.c

194

return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &

sys/dev/drm/radeon/r100.c

447

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/r100.c

452

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/r100.c

453

if (radeon_crtc->enabled) {

sys/dev/drm/radeon/r100.c

454

if (radeon_crtc->crtc_id) {

sys/dev/drm/radeon/r100.c

478

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/r100.c

483

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/r100.c

484

if (radeon_crtc->enabled) {

sys/dev/drm/radeon/r100.c

485

if (radeon_crtc->crtc_id) {

sys/dev/drm/radeon/r600.c

291

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/r600.c

336

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/r600_cs.c

830

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/r600_cs.c

895

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/r600_cs.c

896

crtc_id = radeon_crtc->crtc_id;

sys/dev/drm/radeon/r600_dpm.c

161

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/r600_dpm.c

167

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/r600_dpm.c

168

if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {

sys/dev/drm/radeon/r600_dpm.c

170

radeon_crtc->hw_mode.crtc_htotal *

sys/dev/drm/radeon/r600_dpm.c

171

(radeon_crtc->hw_mode.crtc_vblank_end -

sys/dev/drm/radeon/r600_dpm.c

172

radeon_crtc->hw_mode.crtc_vdisplay +

sys/dev/drm/radeon/r600_dpm.c

173

(radeon_crtc->v_border * 2));

sys/dev/drm/radeon/r600_dpm.c

175

vblank_time_us = vblank_in_pixels * 1000 / radeon_crtc->hw_mode.clock;

sys/dev/drm/radeon/r600_dpm.c

188

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/r600_dpm.c

193

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/r600_dpm.c

194

if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {

sys/dev/drm/radeon/r600_dpm.c

195

vrefresh = drm_mode_vrefresh(&radeon_crtc->hw_mode);

sys/dev/drm/radeon/r600_hdmi.c

319

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/r600_hdmi.c

321

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/drm/radeon/radeon_audio.c

505

struct radeon_crtc *crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/radeon_audio.c

667

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/radeon_audio.c

668

bpc = radeon_crtc->bpc;

sys/dev/drm/radeon/radeon_audio.c

73

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_audio.c

75

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_audio.c

77

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_audio.c

79

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_audio.c

81

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_audio.c

83

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_audio.h

55

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_connectors.c

760

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_connectors.c

762

radeon_crtc->output_csc = radeon_encoder->output_csc;

sys/dev/drm/radeon/radeon_cursor.c

100

lower_32_bits(radeon_crtc->cursor_addr));

sys/dev/drm/radeon/radeon_cursor.c

101

WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/radeon_cursor.c

107

if (radeon_crtc->crtc_id)

sys/dev/drm/radeon/radeon_cursor.c

109

upper_32_bits(radeon_crtc->cursor_addr));

sys/dev/drm/radeon/radeon_cursor.c

112

upper_32_bits(radeon_crtc->cursor_addr));

sys/dev/drm/radeon/radeon_cursor.c

115

WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

116

lower_32_bits(radeon_crtc->cursor_addr));

sys/dev/drm/radeon/radeon_cursor.c

117

WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/radeon_cursor.c

122

WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

123

radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr);

sys/dev/drm/radeon/radeon_cursor.c

125

switch (radeon_crtc->crtc_id) {

sys/dev/drm/radeon/radeon_cursor.c

144

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_cursor.c

147

int w = radeon_crtc->cursor_width;

sys/dev/drm/radeon/radeon_cursor.c

149

radeon_crtc->cursor_x = x;

sys/dev/drm/radeon/radeon_cursor.c

150

radeon_crtc->cursor_y = y;

sys/dev/drm/radeon/radeon_cursor.c

159

xorigin = min(-x, radeon_crtc->max_cursor_width - 1);

sys/dev/drm/radeon/radeon_cursor.c

161

yorigin = min(-y, radeon_crtc->max_cursor_height - 1);

sys/dev/drm/radeon/radeon_cursor.c

207

if (x <= (crtc->x - w) || y <= (crtc->y - radeon_crtc->cursor_height) ||

sys/dev/drm/radeon/radeon_cursor.c

216

WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);

sys/dev/drm/radeon/radeon_cursor.c

217

WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);

sys/dev/drm/radeon/radeon_cursor.c

218

WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

219

((w - 1) << 16) | (radeon_crtc->cursor_height - 1));

sys/dev/drm/radeon/radeon_cursor.c

221

WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);

sys/dev/drm/radeon/radeon_cursor.c

222

WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);

sys/dev/drm/radeon/radeon_cursor.c

223

WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

224

((w - 1) << 16) | (radeon_crtc->cursor_height - 1));

sys/dev/drm/radeon/radeon_cursor.c

232

WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

236

WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

241

WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

242

radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr +

sys/dev/drm/radeon/radeon_cursor.c

246

if (radeon_crtc->cursor_out_of_bounds) {

sys/dev/drm/radeon/radeon_cursor.c

247

radeon_crtc->cursor_out_of_bounds = false;

sys/dev/drm/radeon/radeon_cursor.c

248

if (radeon_crtc->cursor_bo)

sys/dev/drm/radeon/radeon_cursor.c

255

if (!radeon_crtc->cursor_out_of_bounds) {

sys/dev/drm/radeon/radeon_cursor.c

257

radeon_crtc->cursor_out_of_bounds = true;

sys/dev/drm/radeon/radeon_cursor.c

282

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_cursor.c

295

if ((width > radeon_crtc->max_cursor_width) ||

sys/dev/drm/radeon/radeon_cursor.c

296

(height > radeon_crtc->max_cursor_height)) {

sys/dev/drm/radeon/radeon_cursor.c

303

DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_cursor.c

316

(u64 *)&radeon_crtc->cursor_addr);

sys/dev/drm/radeon/radeon_cursor.c

326

if (width != radeon_crtc->cursor_width ||

sys/dev/drm/radeon/radeon_cursor.c

327

height != radeon_crtc->cursor_height ||

sys/dev/drm/radeon/radeon_cursor.c

328

hot_x != radeon_crtc->cursor_hot_x ||

sys/dev/drm/radeon/radeon_cursor.c

329

hot_y != radeon_crtc->cursor_hot_y) {

sys/dev/drm/radeon/radeon_cursor.c

33

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_cursor.c

332

x = radeon_crtc->cursor_x + radeon_crtc->cursor_hot_x - hot_x;

sys/dev/drm/radeon/radeon_cursor.c

333

y = radeon_crtc->cursor_y + radeon_crtc->cursor_hot_y - hot_y;

sys/dev/drm/radeon/radeon_cursor.c

335

radeon_crtc->cursor_width = width;

sys/dev/drm/radeon/radeon_cursor.c

336

radeon_crtc->cursor_height = height;

sys/dev/drm/radeon/radeon_cursor.c

337

radeon_crtc->cursor_hot_x = hot_x;

sys/dev/drm/radeon/radeon_cursor.c

338

radeon_crtc->cursor_hot_y = hot_y;

sys/dev/drm/radeon/radeon_cursor.c

348

if (radeon_crtc->cursor_bo) {

sys/dev/drm/radeon/radeon_cursor.c

349

struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);

sys/dev/drm/radeon/radeon_cursor.c

355

drm_gem_object_put_unlocked(radeon_crtc->cursor_bo);

sys/dev/drm/radeon/radeon_cursor.c

358

radeon_crtc->cursor_bo = obj;

sys/dev/drm/radeon/radeon_cursor.c

37

cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/radeon_cursor.c

372

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_cursor.c

374

if (radeon_crtc->cursor_bo) {

sys/dev/drm/radeon/radeon_cursor.c

377

radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x,

sys/dev/drm/radeon/radeon_cursor.c

378

radeon_crtc->cursor_y);

sys/dev/drm/radeon/radeon_cursor.c

42

WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);

sys/dev/drm/radeon/radeon_cursor.c

44

cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/radeon_cursor.c

49

WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);

sys/dev/drm/radeon/radeon_cursor.c

51

cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/radeon_cursor.c

56

WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);

sys/dev/drm/radeon/radeon_cursor.c

62

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_cursor.c

66

WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

70

WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

74

switch (radeon_crtc->crtc_id) {

sys/dev/drm/radeon/radeon_cursor.c

90

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_cursor.c

93

if (radeon_crtc->cursor_out_of_bounds)

sys/dev/drm/radeon/radeon_cursor.c

97

WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

98

upper_32_bits(radeon_crtc->cursor_addr));

sys/dev/drm/radeon/radeon_cursor.c

99

WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_device.c

1631

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_device.c

1635

if (radeon_crtc->cursor_bo) {

sys/dev/drm/radeon/radeon_device.c

1636

struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);

sys/dev/drm/radeon/radeon_device.c

1768

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_device.c

1770

if (radeon_crtc->cursor_bo) {

sys/dev/drm/radeon/radeon_device.c

1771

struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);

sys/dev/drm/radeon/radeon_device.c

1779

(u64 *)&radeon_crtc->cursor_addr);

sys/dev/drm/radeon/radeon_display.c

100

WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);

sys/dev/drm/radeon/radeon_display.c

102

WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

107

WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

116

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_display.c

122

DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_display.c

126

WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

129

WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

131

WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

133

WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

137

WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

139

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

140

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

141

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

143

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

144

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

145

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

147

WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

148

WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);

sys/dev/drm/radeon/radeon_display.c

150

WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

155

WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

161

WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

166

WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

1686

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_display.c

169

WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

1694

radeon_crtc->h_border = 0;

sys/dev/drm/radeon/radeon_display.c

1695

radeon_crtc->v_border = 0;

sys/dev/drm/radeon/radeon_display.c

1707

radeon_crtc->rmx_type = RMX_OFF;

sys/dev/drm/radeon/radeon_display.c

1710

radeon_crtc->rmx_type = radeon_encoder->rmx_type;

sys/dev/drm/radeon/radeon_display.c

1712

radeon_crtc->rmx_type = RMX_OFF;

sys/dev/drm/radeon/radeon_display.c

1714

memcpy(&radeon_crtc->native_mode,

sys/dev/drm/radeon/radeon_display.c

1718

dst_v = radeon_crtc->native_mode.vdisplay;

sys/dev/drm/radeon/radeon_display.c

172

WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

1720

dst_h = radeon_crtc->native_mode.hdisplay;

sys/dev/drm/radeon/radeon_display.c

173

(NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |

sys/dev/drm/radeon/radeon_display.c

1730

radeon_crtc->h_border = radeon_encoder->underscan_hborder;

sys/dev/drm/radeon/radeon_display.c

1732

radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;

sys/dev/drm/radeon/radeon_display.c

1734

radeon_crtc->v_border = radeon_encoder->underscan_vborder;

sys/dev/drm/radeon/radeon_display.c

1736

radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;

sys/dev/drm/radeon/radeon_display.c

1737

radeon_crtc->rmx_type = RMX_FULL;

sys/dev/drm/radeon/radeon_display.c

1739

dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);

sys/dev/drm/radeon/radeon_display.c

1741

dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);

sys/dev/drm/radeon/radeon_display.c

1745

if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {

sys/dev/drm/radeon/radeon_display.c

1757

if (radeon_crtc->rmx_type != RMX_OFF) {

sys/dev/drm/radeon/radeon_display.c

176

WREG32(0x6940 + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

1761

radeon_crtc->vsc.full = dfixed_div(a, b);

sys/dev/drm/radeon/radeon_display.c

1764

radeon_crtc->hsc.full = dfixed_div(a, b);

sys/dev/drm/radeon/radeon_display.c

1766

radeon_crtc->vsc.full = dfixed_const(1);

sys/dev/drm/radeon/radeon_display.c

1767

radeon_crtc->hsc.full = dfixed_const(1);

sys/dev/drm/radeon/radeon_display.c

181

WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

188

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_display.c

196

if (radeon_crtc->crtc_id == 0)

sys/dev/drm/radeon/radeon_display.c

243

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_display.c

246

destroy_workqueue(radeon_crtc->flip_queue);

sys/dev/drm/radeon/radeon_display.c

247

kfree(radeon_crtc);

sys/dev/drm/radeon/radeon_display.c

280

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/drm/radeon/radeon_display.c

286

if (radeon_crtc == NULL)

sys/dev/drm/radeon/radeon_display.c

302

if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {

sys/dev/drm/radeon/radeon_display.c

305

radeon_crtc->flip_status,

sys/dev/drm/radeon/radeon_display.c

361

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/drm/radeon/radeon_display.c

366

if (radeon_crtc == NULL)

sys/dev/drm/radeon/radeon_display.c

370

work = radeon_crtc->flip_work;

sys/dev/drm/radeon/radeon_display.c

371

if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {

sys/dev/drm/radeon/radeon_display.c

374

radeon_crtc->flip_status,

sys/dev/drm/radeon/radeon_display.c

381

radeon_crtc->flip_status = RADEON_FLIP_NONE;

sys/dev/drm/radeon/radeon_display.c

382

radeon_crtc->flip_work = NULL;

sys/dev/drm/radeon/radeon_display.c

386

drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);

sys/dev/drm/radeon/radeon_display.c

390

drm_crtc_vblank_put(&radeon_crtc->base);

sys/dev/drm/radeon/radeon_display.c

392

queue_work(radeon_crtc->flip_queue, &work->unpin_work);

sys/dev/drm/radeon/radeon_display.c

408

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];

sys/dev/drm/radeon/radeon_display.c

410

struct drm_crtc *crtc = &radeon_crtc->base;

sys/dev/drm/radeon/radeon_display.c

44

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_display.c

449

while (radeon_crtc->enabled &&

sys/dev/drm/radeon/radeon_display.c

464

radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_display.c

467

radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);

sys/dev/drm/radeon/radeon_display.c

469

radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;

sys/dev/drm/radeon/radeon_display.c

483

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_display.c

50

DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_display.c

500

work->crtc_id = radeon_crtc->crtc_id;

sys/dev/drm/radeon/radeon_display.c

51

WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

53

WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

538

base -= radeon_crtc->legacy_display_base_addr;

sys/dev/drm/radeon/radeon_display.c

54

WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

55

WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

57

WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

578

if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {

sys/dev/drm/radeon/radeon_display.c

58

WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

584

radeon_crtc->flip_status = RADEON_FLIP_PENDING;

sys/dev/drm/radeon/radeon_display.c

585

radeon_crtc->flip_work = work;

sys/dev/drm/radeon/radeon_display.c

59

WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

592

queue_work(radeon_crtc->flip_queue, &work->flip_work);

sys/dev/drm/radeon/radeon_display.c

61

WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_display.c

672

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/radeon_display.c

675

radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);

sys/dev/drm/radeon/radeon_display.c

676

if (radeon_crtc == NULL)

sys/dev/drm/radeon/radeon_display.c

679

drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);

sys/dev/drm/radeon/radeon_display.c

681

drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);

sys/dev/drm/radeon/radeon_display.c

682

radeon_crtc->crtc_id = index;

sys/dev/drm/radeon/radeon_display.c

683

radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);

sys/dev/drm/radeon/radeon_display.c

684

rdev->mode_info.crtcs[index] = radeon_crtc;

sys/dev/drm/radeon/radeon_display.c

687

radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;

sys/dev/drm/radeon/radeon_display.c

688

radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;

sys/dev/drm/radeon/radeon_display.c

690

radeon_crtc->max_cursor_width = CURSOR_WIDTH;

sys/dev/drm/radeon/radeon_display.c

691

radeon_crtc->max_cursor_height = CURSOR_HEIGHT;

sys/dev/drm/radeon/radeon_display.c

693

dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;

sys/dev/drm/radeon/radeon_display.c

694

dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;

sys/dev/drm/radeon/radeon_display.c

697

radeon_crtc->mode_set.crtc = &radeon_crtc->base;

sys/dev/drm/radeon/radeon_display.c

698

radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);

sys/dev/drm/radeon/radeon_display.c

699

radeon_crtc->mode_set.num_connectors = 0;

sys/dev/drm/radeon/radeon_display.c

703

radeon_crtc->lut_r[i] = i << 2;

sys/dev/drm/radeon/radeon_display.c

704

radeon_crtc->lut_g[i] = i << 2;

sys/dev/drm/radeon/radeon_display.c

705

radeon_crtc->lut_b[i] = i << 2;

sys/dev/drm/radeon/radeon_display.c

709

radeon_atombios_init_crtc(dev, radeon_crtc);

sys/dev/drm/radeon/radeon_display.c

711

radeon_legacy_init_crtc(dev, radeon_crtc);

sys/dev/drm/radeon/radeon_display.c

77

WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);

sys/dev/drm/radeon/radeon_display.c

82

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_display.c

88

DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_display.c

89

WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

91

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

92

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

93

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

95

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

96

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

97

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

99

WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_dp_mst.c

359

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_dp_mst.c

362

struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);

sys/dev/drm/radeon/radeon_dp_mst.c

371

radeon_crtc->bpc = radeon_connector->base.display_info.bpc;

sys/dev/drm/radeon/radeon_dp_mst.c

373

radeon_crtc->bpc = 8;

sys/dev/drm/radeon/radeon_dp_mst.c

378

radeon_crtc->ss_enabled =

sys/dev/drm/radeon/radeon_dp_mst.c

379

radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,

sys/dev/drm/radeon/radeon_dp_mst.c

394

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/radeon_dp_mst.c

421

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_dp_mst.c

438

mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_dp_mst.c

446

dig_enc->linkb, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_kms.c

261

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_kms.c

262

*value = radeon_crtc->crtc_id;

sys/dev/drm/radeon/radeon_legacy_crtc.c

1037

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_legacy_crtc.c

1044

if (radeon_crtc->crtc_id == 0) {

sys/dev/drm/radeon/radeon_legacy_crtc.c

1047

if (radeon_crtc->rmx_type != RMX_OFF) {

sys/dev/drm/radeon/radeon_legacy_crtc.c

1116

struct radeon_crtc *radeon_crtc)

sys/dev/drm/radeon/radeon_legacy_crtc.c

1118

if (radeon_crtc->crtc_id == 1)

sys/dev/drm/radeon/radeon_legacy_crtc.c

1119

radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;

sys/dev/drm/radeon/radeon_legacy_crtc.c

1120

drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);

sys/dev/drm/radeon/radeon_legacy_crtc.c

126

switch (radeon_crtc->rmx_type) {

sys/dev/drm/radeon/radeon_legacy_crtc.c

296

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_legacy_crtc.c

302

if (radeon_crtc->crtc_id)

sys/dev/drm/radeon/radeon_legacy_crtc.c

324

radeon_crtc->enabled = true;

sys/dev/drm/radeon/radeon_legacy_crtc.c

327

if (radeon_crtc->crtc_id)

sys/dev/drm/radeon/radeon_legacy_crtc.c

334

if (dev->num_crtcs > radeon_crtc->crtc_id)

sys/dev/drm/radeon/radeon_legacy_crtc.c

341

if (dev->num_crtcs > radeon_crtc->crtc_id)

sys/dev/drm/radeon/radeon_legacy_crtc.c

343

if (radeon_crtc->crtc_id)

sys/dev/drm/radeon/radeon_legacy_crtc.c

350

radeon_crtc->enabled = false;

sys/dev/drm/radeon/radeon_legacy_crtc.c

376

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_legacy_crtc.c

39

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_legacy_crtc.c

41

WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_legacy_crtc.c

42

WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_legacy_crtc.c

43

WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_legacy_crtc.c

468

radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;

sys/dev/drm/radeon/radeon_legacy_crtc.c

470

base -= radeon_crtc->legacy_display_base_addr;

sys/dev/drm/radeon/radeon_legacy_crtc.c

51

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_legacy_crtc.c

530

if (radeon_crtc->crtc_id == 1)

sys/dev/drm/radeon/radeon_legacy_crtc.c

543

WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);

sys/dev/drm/radeon/radeon_legacy_crtc.c

546

if (radeon_crtc->crtc_id)

sys/dev/drm/radeon/radeon_legacy_crtc.c

551

WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);

sys/dev/drm/radeon/radeon_legacy_crtc.c

552

WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);

sys/dev/drm/radeon/radeon_legacy_crtc.c

553

WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);

sys/dev/drm/radeon/radeon_legacy_crtc.c

574

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_legacy_crtc.c

593

DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_legacy_crtc.c

63

struct drm_display_mode *native_mode = &radeon_crtc->native_mode;

sys/dev/drm/radeon/radeon_legacy_crtc.c

647

if (radeon_crtc->crtc_id) {

sys/dev/drm/radeon/radeon_legacy_crtc.c

722

WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);

sys/dev/drm/radeon/radeon_legacy_crtc.c

723

WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);

sys/dev/drm/radeon/radeon_legacy_crtc.c

724

WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);

sys/dev/drm/radeon/radeon_legacy_crtc.c

725

WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);

sys/dev/drm/radeon/radeon_legacy_crtc.c

734

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_legacy_crtc.c

770

if (radeon_crtc->crtc_id)

sys/dev/drm/radeon/radeon_legacy_crtc.c

850

if (radeon_crtc->crtc_id) {

sys/dev/drm/radeon/radeon_legacy_encoders.c

1009

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1011

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1157

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1234

if (radeon_crtc->crtc_id == 0) {

sys/dev/drm/radeon/radeon_legacy_encoders.c

1261

if (radeon_crtc->crtc_id == 0) {

sys/dev/drm/radeon/radeon_legacy_encoders.c

1299

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1301

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1547

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1548

if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {

sys/dev/drm/radeon/radeon_legacy_encoders.c

180

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/radeon_legacy_encoders.c

218

if (radeon_crtc->crtc_id == 0) {

sys/dev/drm/radeon/radeon_legacy_encoders.c

239

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_legacy_encoders.c

241

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_legacy_encoders.c

589

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/radeon_legacy_encoders.c

595

if (radeon_crtc->crtc_id == 0) {

sys/dev/drm/radeon/radeon_legacy_encoders.c

635

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_legacy_encoders.c

637

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_legacy_encoders.c

786

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/radeon_legacy_encoders.c

853

if (radeon_crtc->crtc_id == 0) {

sys/dev/drm/radeon/radeon_legacy_encoders.c

875

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_legacy_encoders.c

877

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_legacy_encoders.c

951

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/radeon_legacy_encoders.c

989

if (radeon_crtc->crtc_id == 0) {

sys/dev/drm/radeon/radeon_legacy_tv.c

239

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/radeon_legacy_tv.c

244

radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);

sys/dev/drm/radeon/radeon_legacy_tv.c

245

if (radeon_crtc->crtc_id == 1)

sys/dev/drm/radeon/radeon_legacy_tv.c

427

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/radeon_legacy_tv.c

436

radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);

sys/dev/drm/radeon/radeon_legacy_tv.c

437

if (radeon_crtc->crtc_id == 1)

sys/dev/drm/radeon/radeon_legacy_tv.c

540

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/radeon_legacy_tv.c

557

radeon_crtc = to_radeon_crtc(encoder->crtc);

sys/dev/drm/radeon/radeon_legacy_tv.c

603

if (radeon_crtc->crtc_id == 1)

sys/dev/drm/radeon/radeon_legacy_tv.c

606

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/drm/radeon/radeon_mode.h

247

struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];

sys/dev/drm/radeon/radeon_mode.h

46

#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)

sys/dev/drm/radeon/radeon_mode.h

937

struct radeon_crtc *radeon_crtc);

sys/dev/drm/radeon/radeon_mode.h

939

struct radeon_crtc *radeon_crtc);

sys/dev/drm/radeon/radeon_mode.h

954

void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);

sys/dev/drm/radeon/radeon_pm.c

1733

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/radeon_pm.c

1745

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_pm.c

1746

if (radeon_crtc->enabled) {

sys/dev/drm/radeon/radeon_pm.c

1747

rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_pm.c

1814

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/radeon_pm.c

1829

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/radeon_pm.c

1831

rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_pm.c

1833

if (!radeon_crtc->connector)

sys/dev/drm/radeon/radeon_pm.c

1836

radeon_connector = to_radeon_connector(radeon_crtc->connector);

sys/dev/drm/radeon/rs600.c

114

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/drm/radeon/rs600.c

115

u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/rs600.c

120

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/rs600.c

123

WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/rs600.c

125

WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/rs600.c

127

WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/rs600.c

132

if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)

sys/dev/drm/radeon/rs600.c

140

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/rs600.c

145

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/drm/radeon/rs600.c

148

return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &

sys/dev/drm/radeon/rs600.c

314

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/rs600.c

319

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/rs600.c

320

if (radeon_crtc->enabled) {

sys/dev/drm/radeon/rs600.c

321

tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/rs600.c

323

WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/rs600.c

332

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/rs600.c

337

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/rs600.c

338

if (radeon_crtc->enabled) {

sys/dev/drm/radeon/rs600.c

339

tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/rs600.c

341

WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/rs690.c

271

struct radeon_crtc *crtc,

sys/dev/drm/radeon/rs780_dpm.c

53

struct radeon_crtc *radeon_crtc;

sys/dev/drm/radeon/rs780_dpm.c

63

radeon_crtc = to_radeon_crtc(crtc);

sys/dev/drm/radeon/rs780_dpm.c

64

pi->crtc_id = radeon_crtc->crtc_id;

sys/dev/drm/radeon/rv515.c

706

void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)

sys/dev/drm/radeon/rv515.c

950

struct radeon_crtc *crtc,

sys/dev/drm/radeon/rv770.c

803

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/drm/radeon/rv770.c

804

u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/rv770.c

809

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/rv770.c

812

WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/rv770.c

814

if (radeon_crtc->crtc_id) {

sys/dev/drm/radeon/rv770.c

821

WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/rv770.c

823

WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/rv770.c

828

if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)

sys/dev/drm/radeon/rv770.c

836

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/rv770.c

841

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

sys/dev/drm/radeon/rv770.c

844

return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &

sys/dev/drm/radeon/si.c

1958

struct radeon_crtc *radeon_crtc,

sys/dev/drm/radeon/si.c

1963

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

sys/dev/drm/radeon/si.c

1977

if (radeon_crtc->base.enabled && mode) {

sys/dev/drm/radeon/si.c

1990

WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/si.c

2002

if (radeon_crtc->base.enabled && mode) {

sys/dev/drm/radeon/si.c

2285

struct radeon_crtc *radeon_crtc,

sys/dev/drm/radeon/si.c

2288

struct drm_display_mode *mode = &radeon_crtc->base.mode;

sys/dev/drm/radeon/si.c

2300

if (radeon_crtc->base.enabled && num_heads && mode) {

sys/dev/drm/radeon/si.c

2332

wm_high.vsc = radeon_crtc->vsc;

sys/dev/drm/radeon/si.c

2334

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/drm/radeon/si.c

2359

wm_low.vsc = radeon_crtc->vsc;

sys/dev/drm/radeon/si.c

2361

if (radeon_crtc->rmx_type != RMX_OFF)

sys/dev/drm/radeon/si.c

2397

c.full = dfixed_mul(c, radeon_crtc->hsc);

sys/dev/drm/radeon/si.c

2409

c.full = dfixed_mul(c, radeon_crtc->hsc);

sys/dev/drm/radeon/si.c

2417

radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

sys/dev/drm/radeon/si.c

2421

arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/si.c

2425

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/si.c

2426

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/si.c

2430

tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/si.c

2433

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/si.c

2434

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/si.c

2438

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);

sys/dev/drm/radeon/si.c

2441

WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);

sys/dev/drm/radeon/si.c

2442

WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);

sys/dev/drm/radeon/si.c

2445

radeon_crtc->line_time = line_time;

sys/dev/drm/radeon/si.c

2446

radeon_crtc->wm_high = latency_watermark_a;

sys/dev/drm/radeon/si.c

2447

radeon_crtc->wm_low = latency_watermark_b;

sys/dev/drm/radeon/si_dpm.c

5321

struct radeon_crtc *radeon_crtc = NULL;

sys/dev/drm/radeon/si_dpm.c

5329

radeon_crtc = rdev->mode_info.crtcs[i];

sys/dev/drm/radeon/si_dpm.c

5334

if (radeon_crtc == NULL)

sys/dev/drm/radeon/si_dpm.c

5337

if (radeon_crtc->line_time <= 0)

sys/dev/drm/radeon/si_dpm.c

5342

radeon_crtc->crtc_id) != PPSMC_Result_OK)

sys/dev/drm/radeon/si_dpm.c

5347

radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)

sys/dev/drm/radeon/si_dpm.c

5352

radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)