sys/dev/drm/amd/display/dc/dc_link.h

155

struct psr_context *psr_context);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

156

struct psr_context *psr_context)

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

168

psr_context->psrExitLinkTrainingRequired);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

178

switch (psr_context->controllerId) {

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

216

psr_context->sdpTransmitLineNumDeadline);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

218

if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

228

masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

229

masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

231

psr_context->rfb_update_auto_en;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

232

masterCmdData1.bits.dp_port_num = psr_context->transmitterId;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

233

masterCmdData1.bits.dcp_sel = psr_context->controllerId;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

234

masterCmdData1.bits.phy_type = psr_context->phyType;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

236

psr_context->psrFrameCaptureIndicationReq;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

237

masterCmdData1.bits.aux_chan = psr_context->channel;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

238

masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

243

masterCmdData2.bits.dig_fe = psr_context->engineId;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

244

masterCmdData2.bits.dig_be = psr_context->transmitterId;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

246

psr_context->skipPsrWaitForPllLock;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

247

masterCmdData2.bits.frame_delay = psr_context->frame_delay;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

248

masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

250

psr_context->numberOfControllers;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

255

masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

571

struct psr_context *psr_context)

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

587

psr_context->psrExitLinkTrainingRequired);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

597

switch (psr_context->controllerId) {

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

635

psr_context->sdpTransmitLineNumDeadline);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

637

if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

647

masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

648

masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

650

psr_context->rfb_update_auto_en;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

651

masterCmdData1.bits.dp_port_num = psr_context->transmitterId;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

652

masterCmdData1.bits.dcp_sel = psr_context->controllerId;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

653

masterCmdData1.bits.phy_type = psr_context->phyType;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

655

psr_context->psrFrameCaptureIndicationReq;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

656

masterCmdData1.bits.aux_chan = psr_context->channel;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

657

masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

662

masterCmdData2.bits.dig_fe = psr_context->engineId;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

663

masterCmdData2.bits.dig_be = psr_context->transmitterId;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

665

psr_context->skipPsrWaitForPllLock;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

666

masterCmdData2.bits.frame_delay = psr_context->frame_delay;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

667

masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

669

psr_context->numberOfControllers;

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

674

masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;

sys/dev/drm/amd/display/dc/inc/hw/dmcu.h

53

struct psr_context *psr_context);