pr_info - DragonflyBSD

Symbol: pr_info

sys/dev/drm/amd/amdgpu/amdgpu_device.c

pr_info("amdgpu: switched on\n");

sys/dev/drm/amd/amdgpu/amdgpu_device.c

pr_info("amdgpu: switched off\n");

sys/dev/drm/amd/amdgpu/amdgpu_pm.c

pr_info("manual fan speed control should be enabled first\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("Bad case\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("Invalid BIOS magic\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("Invalid ATI magic\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("Invalid ATOM magic\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("ATOM BIOS: %s\n", str);

sys/dev/drm/amd/amdgpu/atom.c

pr_info("Unknown IIO opcode\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("PCI registers are not implemented\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("SYSIO registers are not implemented\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("Bad IO mode\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("Undefined indirect IO read method %d\n",

sys/dev/drm/amd/amdgpu/atom.c

pr_info("PCI registers are not implemented\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("SYSIO registers are not implemented\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("Bad IO mode\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("Undefined indirect IO write method %d\n",

sys/dev/drm/amd/amdgpu/atom.c

pr_info("unimplemented!\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("unimplemented!\n");

sys/dev/drm/amd/amdgpu/atom.c

pr_info("unimplemented!\n");

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

pr_info("%s", msg);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

pr_info("%pV", &vaf);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

pr_info("%s", msg);

sys/dev/drm/amd/lib/chash.c

pr_info("chash: self test took %llu us, %llu iterations/s\n",

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("Error in phm_get_clock_info \n");

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("force clock level is for dpm manual mode only.\n");

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("power profile setting is for manual dpm mode only.\n");

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/amd_powerplay.c

pr_info("%s was not implemented.\n", __func__);

sys/dev/drm/amd/powerplay/hwmgr/hardwaremanager.c

pr_info("dpm has been disabled\n");

sys/dev/drm/amd/powerplay/hwmgr/hardwaremanager.c

pr_info("dpm has been enabled\n");

sys/dev/drm/amd/powerplay/hwmgr/hwmgr.c

pr_info("dpm not supported \n");

sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

pr_info("Invalid VBIOS AVFS ProfilingInfo Revision!\n");

sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

pr_info("Error retrieving BIOS smu_info Table Address!");

sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

pr_info("Error retrieving BIOS firmwareinfo!");

sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

pr_info("Fw info table revision does not match!");

sys/dev/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

pr_info("Error retrieving BIOS Table Address!");

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

pr_info("smu firmware version too old, can not set dpm level\n");

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

pr_info("Currently sclk only support 3 levels on RV\n");

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

pr_info("Error retrieving EVV voltage value!\n");

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

pr_info("Get EVV Voltage Failed. Abort Driver loading!\n");

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

pr_info("PSPP request to switch to Gen2 from Gen3 Failed!");

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

pr_info("PSPP request to switch to Gen1 from Gen2 Failed!");

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

pr_info("OD voltage is out of range [%d - %d] mV\n",

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

pr_info("OD engine clock is out of range [%d - %d] MHz\n",

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

pr_info("OD memory clock is out of range [%d - %d] MHz\n",

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

pr_info("OverDrive feature not enabled\n");

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

pr_info("invalid clock voltage input \n");

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("Populate LClock Level %d Failed!\n", i);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("Populate LClock Level %d Failed!\n", i);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n");

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("THERMAL Feature Already enabled!");

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("THERMAL Feature Already disabled!");

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("VI should always have 2 performance levels");

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("DPM Table Has Too Many Entries!");

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("Attempt to set Hard Min for DCEFCLK Failed!");

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc);

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("OD engine clock is out of range [%d - %d] MHz\n",

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("OD memory clock is out of range [%d - %d] MHz\n",

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("OverDrive feature not enabled\n");

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("invalid clock voltage input\n");

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

pr_info("Voltage value looks like a Leakage ID but it's not patched\n");

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

pr_info("Number of Pcie Entries exceed the number of"

sys/dev/drm/amd/powerplay/hwmgr/vega10_thermal.c

pr_info("Failed to update Fan Control Table in PPTable!");

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

pr_info("Attempt to set Hard Min for DCEFCLK Failed!");

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("Attempt to set Hard Min for DCEFCLK Failed!");

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("Sclk min/max frequency overdrive not supported\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("invalid number of input parameters %d\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("Invalid index %d\n", input_index);

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("Support min/max sclk frequency setting only which index by 0/1\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("clock freq %d is not within allowed range [%d - %d]\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("Mclk max frequency overdrive not supported\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("invalid number of input parameters %d\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("Invalid index %d\n", input_index);

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("Support max Mclk frequency setting only which index by 1\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("clock freq %d is not within allowed range [%d - %d]\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("Voltage curve calibrate not supported\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("invalid number of input parameters %d\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("Setting for point %d is not supported\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("Three supported points index by 0, 1, 2\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("clock freq %d is not within allowed range [%d - %d]\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("clock voltage %d is not within allowed range [%d - %d]\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("MemoryOnPackage = 0x%02x\n", pptable->MemoryOnPackage);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("padding8_limits = 0x%02x\n", pptable->padding8_limits);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Tvr_SocLimit = %d\n", pptable->Tvr_SocLimit);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("UlvVoltageOffsetSoc = %d\n", pptable->UlvVoltageOffsetSoc);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("UlvSmnclkDid = %d\n", pptable->UlvSmnclkDid);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("UlvMp1clkDid = %d\n", pptable->UlvMp1clkDid);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding234 = 0x%02x\n", pptable->Padding234);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("[PPCLK_GFXCLK]\n"

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("[PPCLK_VCLK]\n"

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("[PPCLK_DCLK]\n"

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("[PPCLK_ECLK]\n"

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("[PPCLK_SOCCLK]\n"

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("[PPCLK_UCLK]\n"

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("[PPCLK_DCEFCLK]\n"

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("[PPCLK_DISPCLK]\n"

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("[PPCLK_PIXCLK]\n"

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("[PPCLK_PHYCLK]\n"

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("[PPCLK_FCLK]\n"

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FreqTableGfx\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FreqTableVclk\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FreqTableDclk\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FreqTableEclk\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%02d] = %d\n", i, pptable->FreqTableEclk[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FreqTableSocclk\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FreqTableUclk\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FreqTableFclk\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FreqTableDcefclk\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDcefclk[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FreqTableDispclk\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%02d] = %d\n", i, pptable->FreqTableDispclk[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FreqTablePixclk\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%02d] = %d\n", i, pptable->FreqTablePixclk[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FreqTablePhyclk\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%02d] = %d\n", i, pptable->FreqTablePhyclk[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcModeMaxFreq[PPCLK_GFXCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcModeMaxFreq[PPCLK_VCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_VCLK]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcModeMaxFreq[PPCLK_DCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_DCLK]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcModeMaxFreq[PPCLK_ECLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_ECLK]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcModeMaxFreq[PPCLK_SOCCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcModeMaxFreq[PPCLK_UCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcModeMaxFreq[PPCLK_DCEFCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_DCEFCLK]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcModeMaxFreq[PPCLK_DISPCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_DISPCLK]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcModeMaxFreq[PPCLK_PIXCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_PIXCLK]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcModeMaxFreq[PPCLK_PHYCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_PHYCLK]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcModeMaxFreq[PPCLK_FCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding8_Clks = %d\n", pptable->Padding8_Clks);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Mp0clkFreq\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Mp0DpmVoltage\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("CksEnableFreq = 0x%x\n", pptable->CksEnableFreq);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding789 = 0x%x\n", pptable->Padding789);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("CksVoltageOffset[a = 0x%08x b = 0x%08x c = 0x%08x]\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding456 = 0x%x\n", pptable->Padding456);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("LowestUclkReservedForUlv = %d\n", pptable->LowestUclkReservedForUlv);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding8_Uclk[0] = 0x%x\n", pptable->Padding8_Uclk[0]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding8_Uclk[1] = 0x%x\n", pptable->Padding8_Uclk[1]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding8_Uclk[2] = 0x%x\n", pptable->Padding8_Uclk[2]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("PcieGenSpeed\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%d] = %d\n", i, pptable->PcieGenSpeed[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("PcieLaneCount\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%d] = %d\n", i, pptable->PcieLaneCount[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("LclkFreq\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%d] = %d\n", i, pptable->LclkFreq[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanGainLiquid = %d\n", pptable->FanGainLiquid);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanGainPlx = %d\n", pptable->FanGainPlx);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("dBtcGbGfxCksOn{a = 0x%x b = 0x%x c = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("dBtcGbGfxCksOff{a = 0x%x b = 0x%x c = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("XgmiLinkSpeed\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("XgmiLinkWidth\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("XgmiFclkFreq\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("XgmiUclkFreq\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%d] = %d\n", i, pptable->XgmiUclkFreq[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("XgmiSocclkFreq\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%d] = %d\n", i, pptable->XgmiSocclkFreq[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("XgmiSocVoltage\n");

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("MinVoltageUlvSoc = %d\n", pptable->MinVoltageUlvSoc);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("MGpuFanBoostLimitRpm = %d\n", pptable->MGpuFanBoostLimitRpm);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("padding16_Fan = %d\n", pptable->padding16_Fan);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanGainVrMem0 = %d\n", pptable->FanGainVrMem0);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FanGainVrMem0 = %d\n", pptable->FanGainVrMem0);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Reserved[%d] = 0x%x\n", i, pptable->Reserved[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding32[%d] = 0x%x\n", i, pptable->Padding32[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding8_V = 0x%x\n", pptable->Padding8_V);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("SocOffset = 0x%x\n", pptable->SocOffset);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("AcDcGpio = %d\n", pptable->AcDcGpio);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("AcDcPolarity = %d\n", pptable->AcDcPolarity);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding1 = 0x%x\n", pptable->Padding1);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Padding2 = 0x%x\n", pptable->Padding2);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("LedPin0 = %d\n", pptable->LedPin0);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("LedPin1 = %d\n", pptable->LedPin1);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("LedPin2 = %d\n", pptable->LedPin2);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("padding8_4 = 0x%x\n", pptable->padding8_4);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("I2cControllers[%d]:\n", i);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .Enabled = %d\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .SlaveAddress = 0x%x\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .ControllerPort = %d\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .ControllerName = %d\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .ThermalThrottler = %d\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .I2cProtocol = %d\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info(" .I2cSpeed = %d\n",

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("BoardReserved[%d] = 0x%x\n", i, pptable->BoardReserved[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("MmHubPadding[%d] = 0x%x\n", i, pptable->MmHubPadding[i]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Unmatch PPTable version: "

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Version = 0x%08x\n", pptable->Version);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("SocketPowerLimitAc0 = %d\n", pptable->SocketPowerLimitAc0);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("SocketPowerLimitAc0Tau = %d\n", pptable->SocketPowerLimitAc0Tau);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("SocketPowerLimitAc1 = %d\n", pptable->SocketPowerLimitAc1);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("SocketPowerLimitAc1Tau = %d\n", pptable->SocketPowerLimitAc1Tau);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("SocketPowerLimitAc2 = %d\n", pptable->SocketPowerLimitAc2);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("SocketPowerLimitAc2Tau = %d\n", pptable->SocketPowerLimitAc2Tau);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("SocketPowerLimitAc3 = %d\n", pptable->SocketPowerLimitAc3);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("SocketPowerLimitAc3Tau = %d\n", pptable->SocketPowerLimitAc3Tau);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("SocketPowerLimitDc = %d\n", pptable->SocketPowerLimitDc);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("SocketPowerLimitDcTau = %d\n", pptable->SocketPowerLimitDcTau);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("ThbmLimit = %d\n", pptable->ThbmLimit);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Tliquid1Limit = %d\n", pptable->Tliquid1Limit);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("Tliquid2Limit = %d\n", pptable->Tliquid2Limit);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("TplxLimit = %d\n", pptable->TplxLimit);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("FitLimit = %d\n", pptable->FitLimit);

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

pr_info("VDDCshould be on SVI2 controller!");

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

pr_info("\n failed to send message %x ret is %d\n", msg, ret);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

pr_info("smc is running, no need to load smc firmware\n");

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

pr_info("Engine clock can't satisfy stutter requirement!\n");

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed");

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

pr_info("smu not running, upload firmware again \n");

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

pr_info("\n last message was failed ret is %d\n", ret);

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

pr_info("\n failed to send message %x ret is %d \n", msg, ret);

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

pr_info("Failed to send Message.\n");

sys/dev/drm/i915/i915_drv.c

pr_info("switched on\n");

sys/dev/drm/i915/i915_drv.c

pr_info("switched off\n");

sys/dev/drm/i915/i915_gem_shrinker.c

pr_info("Purging GPU memory, %lu pages freed, "

sys/dev/drm/radeon/evergreen_cs.c

pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);

sys/dev/drm/radeon/evergreen_cs.c

pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);

sys/dev/drm/radeon/r600_cs.c

pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);

sys/dev/drm/radeon/r600_cs.c

pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);

sys/dev/drm/radeon/radeon_device.c

pr_info("radeon: switched on\n");

sys/dev/drm/radeon/radeon_device.c

pr_info("radeon: switched off\n");

sys/dev/drm/ttm/ttm_memory.c

pr_info("Zone %7s: Available graphics memory: %llu kiB\n",

sys/dev/drm/ttm/ttm_memory.c

pr_info("Zone %7s: Used memory at exit: %llu kiB\n",

sys/dev/drm/ttm/ttm_page_alloc.c

pr_info("Initializing pool allocator\n");

sys/dev/drm/ttm/ttm_page_alloc.c

pr_info("Finalizing pool allocator\n");

sys/dev/drm/ttm/ttm_page_alloc_dma.c

pr_info("Initializing DMA pool allocator\n");

sys/dev/drm/ttm/ttm_page_alloc_dma.c

pr_info("Finalizing DMA pool allocator\n");

sys/dev/video/vga/vga_switcheroo.c

pr_info("setting delayed switch to client %d\n", client->id);

sys/dev/video/vga/vga_switcheroo.c

pr_info("processing delayed switch to %d\n",

sys/dev/video/vga/vga_switcheroo.c

pr_info("enabled\n");

sys/dev/video/vga/vga_switcheroo.c

pr_info("disabled\n");

sys/dev/video/vga/vga_switcheroo.c

pr_info("enabled\n");

sys/dev/video/vga/vga_switcheroo.c

pr_info("disabled\n");

sys/dev/video/vga/vga_switcheroo.c

pr_info("setting delayed switch to client %d\n", client->id);