pmu
struct i915_pmu pmu;
ret = cpuhp_state_add_instance(slot, &i915->pmu.node);
WARN_ON(cpuhp_state_remove_instance(cpuhp_slot, &i915->pmu.node));
i915->pmu.base.attr_groups = i915_pmu_attr_groups;
i915->pmu.base.task_ctx_nr = perf_invalid_context;
i915->pmu.base.event_init = i915_pmu_event_init;
i915->pmu.base.add = i915_pmu_event_add;
i915->pmu.base.del = i915_pmu_event_del;
i915->pmu.base.start = i915_pmu_event_start;
i915->pmu.base.stop = i915_pmu_event_stop;
i915->pmu.base.read = i915_pmu_event_read;
i915->pmu.base.event_idx = i915_pmu_event_event_idx;
spin_lock_init(&i915->pmu.lock);
hrtimer_init(&i915->pmu.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
i915->pmu.timer.function = i915_sample;
ret = perf_pmu_register(&i915->pmu.base, "i915", -1);
perf_pmu_unregister(&i915->pmu.base);
i915->pmu.base.event_init = NULL;
if (!i915->pmu.base.event_init)
WARN_ON(i915->pmu.enable);
hrtimer_cancel(&i915->pmu.timer);
perf_pmu_unregister(&i915->pmu.base);
i915->pmu.base.event_init = NULL;
if (!i915->pmu.base.event_init)
spin_lock_irq(&i915->pmu.lock);
i915->pmu.timer_enabled = pmu_needs_timer(i915, false);
spin_unlock_irq(&i915->pmu.lock);
if (!i915->pmu.timer_enabled && pmu_needs_timer(i915, true)) {
i915->pmu.timer_enabled = true;
i915->pmu.timer_last = ktime_get();
hrtimer_start_range_ns(&i915->pmu.timer,
if (!i915->pmu.base.event_init)
spin_lock_irq(&i915->pmu.lock);
spin_unlock_irq(&i915->pmu.lock);
if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
add_sample(&engine->pmu.sample[I915_SAMPLE_BUSY],
if (val && (engine->pmu.enable &
add_sample(&engine->pmu.sample[I915_SAMPLE_WAIT],
add_sample(&engine->pmu.sample[I915_SAMPLE_SEMA],
if (dev_priv->pmu.enable &
add_sample_mult(&dev_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT],
if (dev_priv->pmu.enable &
add_sample_mult(&dev_priv->pmu.sample[__I915_SAMPLE_FREQ_REQ],
container_of(hrtimer, struct drm_i915_private, pmu.timer);
if (!READ_ONCE(i915->pmu.timer_enabled))
period_ns = ktime_to_ns(ktime_sub(now, i915->pmu.timer_last));
i915->pmu.timer_last = now;
container_of(event->pmu, typeof(*i915), pmu.base);
container_of(event->pmu, typeof(*i915), pmu.base);
container_of(event->pmu, typeof(*i915), pmu.base);
if (event->attr.type != event->pmu->type)
spin_lock_irqsave(&i915->pmu.lock, flags);
if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;
val = i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur;
spin_unlock_irqrestore(&i915->pmu.lock, flags);
spin_lock_irqsave(&i915->pmu.lock, flags);
if (!i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur)
i915->pmu.suspended_jiffies_last =
i915->pmu.suspended_jiffies_last;
val += i915->pmu.sample[__I915_SAMPLE_RC6].cur;
i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val;
} else if (i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
val = i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur;
val = i915->pmu.sample[__I915_SAMPLE_RC6].cur;
spin_unlock_irqrestore(&i915->pmu.lock, flags);
container_of(event->pmu, typeof(*i915), pmu.base);
val = engine->pmu.sample[sample].cur;
div_u64(i915->pmu.sample[__I915_SAMPLE_FREQ_ACT].cur,
div_u64(i915->pmu.sample[__I915_SAMPLE_FREQ_REQ].cur,
container_of(event->pmu, typeof(*i915), pmu.base);
spin_lock_irqsave(&i915->pmu.lock, flags);
GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0);
i915->pmu.enable |= BIT_ULL(bit);
i915->pmu.enable_count[bit]++;
engine->pmu.enable |= BIT(sample);
GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
engine->pmu.enable_count[sample]++;
spin_unlock_irqrestore(&i915->pmu.lock, flags);
container_of(event->pmu, typeof(*i915), pmu.base);
spin_lock_irqsave(&i915->pmu.lock, flags);
GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
if (--engine->pmu.enable_count[sample] == 0)
engine->pmu.enable &= ~BIT(sample);
GEM_BUG_ON(i915->pmu.enable_count[bit] == 0);
if (--i915->pmu.enable_count[bit] == 0) {
i915->pmu.enable &= ~BIT_ULL(bit);
i915->pmu.timer_enabled &= pmu_needs_timer(i915, true);
spin_unlock_irqrestore(&i915->pmu.lock, flags);
enable = i915->pmu.enable;
i915->pmu.i915_attr = i915_attr;
i915->pmu.pmu_attr = pmu_attr;
kfree(i915->pmu.i915_attr);
kfree(i915->pmu.pmu_attr);
i915->pmu.i915_attr = NULL;
i915->pmu.pmu_attr = NULL;
struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node);
GEM_BUG_ON(!pmu->base.event_init);
struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node);
GEM_BUG_ON(!pmu->base.event_init);
perf_pmu_migrate_context(&pmu->base, cpu, target);
struct pmu base;
} pmu;
uint32_t bufsth = 0, pll, pmu;
pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
if (SIBA_CC_PMUCTL_XF_VAL(pmu) == e->xf)
pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
pmu &= ~(SIBA_CC_PMUCTL_ILP | SIBA_CC_PMUCTL_XF);
pmu |= ((((uint32_t)e->freq + 127) / 128 - 1) << 16) &
pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF;
SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
uint32_t pmu, tmp, pll;
pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
if (((pmu & SIBA_CC_PMUCTL_XF) >> 2) == e->xf)
pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL);
pmu &= ~SIBA_CC_PMUCTL_ILP;
pmu |= (((xtalfreq + 127) / 128 - 1) << 16) & SIBA_CC_PMUCTL_ILP;
pmu &= ~SIBA_CC_PMUCTL_XF;
pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF;
SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu);
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
phbbmu = (struct HBB_MessageUnit *)acb->pmu;
phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
acb->pmu = (struct MessageUnit_UNION *)mem_base0;
acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
phbbmu = (struct HBB_MessageUnit *)acb->pmu;
acb->pmu = (struct MessageUnit_UNION *)mem_base0;
acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
acb->pmu = (struct MessageUnit_UNION *)mem_base0;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */