sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1737

int plane_id)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1744

mode_info->planes[plane_id] = plane;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1750

plane->base.type = mode_info->plane_type[plane_id];

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1758

possible_crtcs = 1 << plane_id;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1759

if (plane_id >= dm->dc->caps.max_streams)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1762

ret = amdgpu_dm_plane_init(dm, mode_info->planes[plane_id], possible_crtcs);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

524

int plane_id)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

530

dpp_pg_control(hws, plane_id, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

531

hubp_pg_control(hws, plane_id, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

535

"Un-gated front end for pipe %d\n", plane_id);

sys/dev/drm/drm_plane.c

519

plane = drm_plane_find(dev, file_priv, plane_resp->plane_id);

sys/dev/drm/drm_plane.c

539

plane_resp->plane_id = plane->base.id;

sys/dev/drm/drm_plane.c

790

plane = drm_plane_find(dev, file_priv, plane_req->plane_id);

sys/dev/drm/drm_plane.c

793

plane_req->plane_id);

sys/dev/drm/i915/i915_drv.h

2248

#define INTEL_FRONTBUFFER(pipe, plane_id) ({ \

sys/dev/drm/i915/i915_drv.h

2251

BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \

sys/dev/drm/i915/i915_reg.h

6435

#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \

sys/dev/drm/i915/i915_reg.h

6436

_MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))

sys/dev/drm/i915/i915_reg.h

6438

#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)

sys/dev/drm/i915/i915_reg.h

6439

#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)

sys/dev/drm/i915/i915_reg.h

6440

#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)

sys/dev/drm/i915/i915_reg.h

6441

#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)

sys/dev/drm/i915/i915_reg.h

6442

#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)

sys/dev/drm/i915/i915_reg.h

6443

#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)

sys/dev/drm/i915/i915_reg.h

6444

#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)

sys/dev/drm/i915/i915_reg.h

6445

#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)

sys/dev/drm/i915/i915_reg.h

6446

#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)

sys/dev/drm/i915/i915_reg.h

6447

#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)

sys/dev/drm/i915/i915_reg.h

6448

#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)

sys/dev/drm/i915/i915_reg.h

6449

#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)

sys/dev/drm/i915/i915_reg.h

6450

#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)

sys/dev/drm/i915/i915_reg.h

6451

#define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)

sys/dev/drm/i915/i915_reg.h

6460

#define _MMIO_CHV_SPCSC(plane_id, reg) \

sys/dev/drm/i915/i915_reg.h

6461

_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))

sys/dev/drm/i915/i915_reg.h

6463

#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)

sys/dev/drm/i915/i915_reg.h

6464

#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)

sys/dev/drm/i915/i915_reg.h

6465

#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)

sys/dev/drm/i915/i915_reg.h

6469

#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)

sys/dev/drm/i915/i915_reg.h

6470

#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)

sys/dev/drm/i915/i915_reg.h

6471

#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)

sys/dev/drm/i915/i915_reg.h

6472

#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)

sys/dev/drm/i915/i915_reg.h

6473

#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)

sys/dev/drm/i915/i915_reg.h

6477

#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)

sys/dev/drm/i915/i915_reg.h

6478

#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)

sys/dev/drm/i915/i915_reg.h

6479

#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)

sys/dev/drm/i915/i915_reg.h

6483

#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)

sys/dev/drm/i915/i915_reg.h

6484

#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)

sys/dev/drm/i915/i915_reg.h

6485

#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)

sys/dev/drm/i915/intel_display.c

13766

enum i915_pipe pipe, enum plane_id plane_id)

sys/dev/drm/i915/intel_display.c

13771

return pipe == PIPE_A && plane_id == PLANE_PRIMARY;

sys/dev/drm/i915/intel_display.c

13775

enum i915_pipe pipe, enum plane_id plane_id)

sys/dev/drm/i915/intel_display.c

13790

if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)

sys/dev/drm/i915/intel_display.c

8895

enum plane_id plane_id = plane->id;

sys/dev/drm/i915/intel_display.c

8918

val = I915_READ(PLANE_CTL(pipe, plane_id));

sys/dev/drm/i915/intel_display.c

8926

alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));

sys/dev/drm/i915/intel_display.c

8986

base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;

sys/dev/drm/i915/intel_display.c

8989

offset = I915_READ(PLANE_OFFSET(pipe, plane_id));

sys/dev/drm/i915/intel_display.c

8991

val = I915_READ(PLANE_SIZE(pipe, plane_id));

sys/dev/drm/i915/intel_display.c

8995

val = I915_READ(PLANE_STRIDE(pipe, plane_id));

sys/dev/drm/i915/intel_drv.h

2151

enum i915_pipe pipe, enum plane_id plane_id);

sys/dev/drm/i915/intel_drv.h

2153

enum i915_pipe pipe, enum plane_id plane_id);

sys/dev/drm/i915/intel_drv.h

967

enum plane_id id;

sys/dev/drm/i915/intel_pm.c

1048

static int g4x_plane_fifo_size(enum plane_id plane_id, int level)

sys/dev/drm/i915/intel_pm.c

1064

switch (plane_id) {

sys/dev/drm/i915/intel_pm.c

1072

MISSING_CASE(plane_id);

sys/dev/drm/i915/intel_pm.c

1155

int level, enum plane_id plane_id, u16 value)

sys/dev/drm/i915/intel_pm.c

1163

dirty |= raw->plane[plane_id] != value;

sys/dev/drm/i915/intel_pm.c

1164

raw->plane[plane_id] = value;

sys/dev/drm/i915/intel_pm.c

1198

enum plane_id plane_id = plane->id;

sys/dev/drm/i915/intel_pm.c

1203

dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);

sys/dev/drm/i915/intel_pm.c

1204

if (plane_id == PLANE_PRIMARY)

sys/dev/drm/i915/intel_pm.c

1214

max_wm = g4x_plane_fifo_size(plane_id, level);

sys/dev/drm/i915/intel_pm.c

1219

dirty |= raw->plane[plane_id] != wm;

sys/dev/drm/i915/intel_pm.c

1220

raw->plane[plane_id] = wm;

sys/dev/drm/i915/intel_pm.c

1222

if (plane_id != PLANE_PRIMARY ||

sys/dev/drm/i915/intel_pm.c

1227

raw->plane[plane_id]);

sys/dev/drm/i915/intel_pm.c

1242

dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);

sys/dev/drm/i915/intel_pm.c

1244

if (plane_id == PLANE_PRIMARY)

sys/dev/drm/i915/intel_pm.c

1251

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],

sys/dev/drm/i915/intel_pm.c

1252

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],

sys/dev/drm/i915/intel_pm.c

1253

crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);

sys/dev/drm/i915/intel_pm.c

1255

if (plane_id == PLANE_PRIMARY)

sys/dev/drm/i915/intel_pm.c

1265

enum plane_id plane_id, int level)

sys/dev/drm/i915/intel_pm.c

1269

return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);

sys/dev/drm/i915/intel_pm.c

1290

enum plane_id plane_id;

sys/dev/drm/i915/intel_pm.c

1292

for_each_plane_id_on_crtc(crtc, plane_id)

sys/dev/drm/i915/intel_pm.c

1293

wm_state->wm.plane[plane_id] = USHRT_MAX;

sys/dev/drm/i915/intel_pm.c

1323

enum plane_id plane_id;

sys/dev/drm/i915/intel_pm.c

1346

for_each_plane_id_on_crtc(crtc, plane_id)

sys/dev/drm/i915/intel_pm.c

1347

wm_state->wm.plane[plane_id] = raw->plane[plane_id];

sys/dev/drm/i915/intel_pm.c

1411

enum plane_id plane_id;

sys/dev/drm/i915/intel_pm.c

1427

for_each_plane_id_on_crtc(crtc, plane_id) {

sys/dev/drm/i915/intel_pm.c

1428

intermediate->wm.plane[plane_id] =

sys/dev/drm/i915/intel_pm.c

1429

max(optimal->wm.plane[plane_id],

sys/dev/drm/i915/intel_pm.c

1430

active->wm.plane[plane_id]);

sys/dev/drm/i915/intel_pm.c

1432

WARN_ON(intermediate->wm.plane[plane_id] >

sys/dev/drm/i915/intel_pm.c

1433

g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));

sys/dev/drm/i915/intel_pm.c

1655

enum plane_id plane_id;

sys/dev/drm/i915/intel_pm.c

1679

for_each_plane_id_on_crtc(crtc, plane_id) {

sys/dev/drm/i915/intel_pm.c

1682

if ((active_planes & BIT(plane_id)) == 0) {

sys/dev/drm/i915/intel_pm.c

1683

fifo_state->plane[plane_id] = 0;

sys/dev/drm/i915/intel_pm.c

1687

rate = raw->plane[plane_id];

sys/dev/drm/i915/intel_pm.c

1688

fifo_state->plane[plane_id] = fifo_size * rate / total_rate;

sys/dev/drm/i915/intel_pm.c

1689

fifo_left -= fifo_state->plane[plane_id];

sys/dev/drm/i915/intel_pm.c

1700

for_each_plane_id_on_crtc(crtc, plane_id) {

sys/dev/drm/i915/intel_pm.c

1706

if ((active_planes & BIT(plane_id)) == 0)

sys/dev/drm/i915/intel_pm.c

1710

fifo_state->plane[plane_id] += plane_extra;

sys/dev/drm/i915/intel_pm.c

1732

enum plane_id plane_id;

sys/dev/drm/i915/intel_pm.c

1734

for_each_plane_id_on_crtc(crtc, plane_id)

sys/dev/drm/i915/intel_pm.c

1735

wm_state->wm[level].plane[plane_id] = USHRT_MAX;

sys/dev/drm/i915/intel_pm.c

1755

int level, enum plane_id plane_id, u16 value)

sys/dev/drm/i915/intel_pm.c

1764

dirty |= raw->plane[plane_id] != value;

sys/dev/drm/i915/intel_pm.c

1765

raw->plane[plane_id] = value;

sys/dev/drm/i915/intel_pm.c

1775

enum plane_id plane_id = plane->id;

sys/dev/drm/i915/intel_pm.c

1781

dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);

sys/dev/drm/i915/intel_pm.c

1788

int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;

sys/dev/drm/i915/intel_pm.c

1793

dirty |= raw->plane[plane_id] != wm;

sys/dev/drm/i915/intel_pm.c

1794

raw->plane[plane_id] = wm;

sys/dev/drm/i915/intel_pm.c

1798

dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);

sys/dev/drm/i915/intel_pm.c

1804

crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],

sys/dev/drm/i915/intel_pm.c

1805

crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],

sys/dev/drm/i915/intel_pm.c

1806

crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);

sys/dev/drm/i915/intel_pm.c

1812

enum plane_id plane_id, int level)

sys/dev/drm/i915/intel_pm.c

1819

return raw->plane[plane_id] <= fifo_state->plane[plane_id];

sys/dev/drm/i915/intel_pm.c

1845

enum plane_id plane_id;

sys/dev/drm/i915/intel_pm.c

1905

for_each_plane_id_on_crtc(crtc, plane_id) {

sys/dev/drm/i915/intel_pm.c

1906

wm_state->wm[level].plane[plane_id] =

sys/dev/drm/i915/intel_pm.c

1907

vlv_invert_wm_value(raw->plane[plane_id],

sys/dev/drm/i915/intel_pm.c

1908

fifo_state->plane[plane_id]);

sys/dev/drm/i915/intel_pm.c

2058

enum plane_id plane_id;

sys/dev/drm/i915/intel_pm.c

2060

for_each_plane_id_on_crtc(crtc, plane_id) {

sys/dev/drm/i915/intel_pm.c

2061

intermediate->wm[level].plane[plane_id] =

sys/dev/drm/i915/intel_pm.c

2062

min(optimal->wm[level].plane[plane_id],

sys/dev/drm/i915/intel_pm.c

2063

active->wm[level].plane[plane_id]);

sys/dev/drm/i915/intel_pm.c

3958

const enum plane_id plane_id,

sys/dev/drm/i915/intel_pm.c

3965

if (plane_id == PLANE_CURSOR) {

sys/dev/drm/i915/intel_pm.c

3968

&ddb->plane[pipe][plane_id], val);

sys/dev/drm/i915/intel_pm.c

3972

val = I915_READ(PLANE_CTL(pipe, plane_id));

sys/dev/drm/i915/intel_pm.c

3983

val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));

sys/dev/drm/i915/intel_pm.c

3989

val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));

sys/dev/drm/i915/intel_pm.c

3993

&ddb->plane[pipe][plane_id], val2);

sys/dev/drm/i915/intel_pm.c

3995

&ddb->uv_plane[pipe][plane_id], val);

sys/dev/drm/i915/intel_pm.c

3998

&ddb->plane[pipe][plane_id], val);

sys/dev/drm/i915/intel_pm.c

4013

enum plane_id plane_id;

sys/dev/drm/i915/intel_pm.c

4020

for_each_plane_id_on_crtc(crtc, plane_id)

sys/dev/drm/i915/intel_pm.c

4022

plane_id, ddb);

sys/dev/drm/i915/intel_pm.c

4244

enum plane_id plane_id = to_intel_plane(plane)->id;

sys/dev/drm/i915/intel_pm.c

4250

plane_data_rate[plane_id] = rate;

sys/dev/drm/i915/intel_pm.c

4257

uv_plane_data_rate[plane_id] = rate;

sys/dev/drm/i915/intel_pm.c

4336

enum plane_id plane_id = to_intel_plane(plane)->id;

sys/dev/drm/i915/intel_pm.c

4338

if (plane_id == PLANE_CURSOR)

sys/dev/drm/i915/intel_pm.c

4344

minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);

sys/dev/drm/i915/intel_pm.c

4345

uv_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);

sys/dev/drm/i915/intel_pm.c

4365

enum plane_id plane_id;

sys/dev/drm/i915/intel_pm.c

4400

for_each_plane_id_on_crtc(intel_crtc, plane_id) {

sys/dev/drm/i915/intel_pm.c

4401

total_min_blocks += minimum[plane_id];

sys/dev/drm/i915/intel_pm.c

4402

total_min_blocks += uv_minimum[plane_id];

sys/dev/drm/i915/intel_pm.c

4426

for_each_plane_id_on_crtc(intel_crtc, plane_id) {

sys/dev/drm/i915/intel_pm.c

4430

if (plane_id == PLANE_CURSOR)

sys/dev/drm/i915/intel_pm.c

4433

data_rate = plane_data_rate[plane_id];

sys/dev/drm/i915/intel_pm.c

4440

plane_blocks = minimum[plane_id];

sys/dev/drm/i915/intel_pm.c

4446

ddb->plane[pipe][plane_id].start = start;

sys/dev/drm/i915/intel_pm.c

4447

ddb->plane[pipe][plane_id].end = start + plane_blocks;

sys/dev/drm/i915/intel_pm.c

4453

uv_data_rate = uv_plane_data_rate[plane_id];

sys/dev/drm/i915/intel_pm.c

4455

uv_plane_blocks = uv_minimum[plane_id];

sys/dev/drm/i915/intel_pm.c

4460

ddb->uv_plane[pipe][plane_id].start = start;

sys/dev/drm/i915/intel_pm.c

4461

ddb->uv_plane[pipe][plane_id].end =

sys/dev/drm/i915/intel_pm.c

4561

struct skl_wm_params *wp, int plane_id)

sys/dev/drm/i915/intel_pm.c

4575

if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {

sys/dev/drm/i915/intel_pm.c

4600

if (plane_id == 1 && wp->is_planar)

sys/dev/drm/i915/intel_pm.c

4603

wp->cpp = fb->format->cpp[plane_id];

sys/dev/drm/i915/intel_pm.c

4821

int plane_id)

sys/dev/drm/i915/intel_pm.c

4829

enum plane_id intel_plane_id = intel_plane->id;

sys/dev/drm/i915/intel_pm.c

4835

ddb_blocks = plane_id ?

sys/dev/drm/i915/intel_pm.c

4840

struct skl_wm_level *result = plane_id ? &wm->uv_wm[level] :

sys/dev/drm/i915/intel_pm.c

4845

result_prev = plane_id ? &wm->uv_wm[level - 1] :

sys/dev/drm/i915/intel_pm.c

4848

result_prev = plane_id ? &wm->uv_wm[0] : &wm->wm[0];

sys/dev/drm/i915/intel_pm.c

4967

enum plane_id plane_id = to_intel_plane(plane)->id;

sys/dev/drm/i915/intel_pm.c

4972

wm = &pipe_wm->planes[plane_id];

sys/dev/drm/i915/intel_pm.c

4973

ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);

sys/dev/drm/i915/intel_pm.c

5040

enum plane_id plane_id)

sys/dev/drm/i915/intel_pm.c

5049

skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),

sys/dev/drm/i915/intel_pm.c

5052

skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),

sys/dev/drm/i915/intel_pm.c

5055

skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),

sys/dev/drm/i915/intel_pm.c

5056

&ddb->plane[pipe][plane_id]);

sys/dev/drm/i915/intel_pm.c

5060

PLANE_BUF_CFG(pipe, plane_id),

sys/dev/drm/i915/intel_pm.c

5061

&ddb->plane[pipe][plane_id]);

sys/dev/drm/i915/intel_pm.c

5063

skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),

sys/dev/drm/i915/intel_pm.c

5064

&ddb->uv_plane[pipe][plane_id]);

sys/dev/drm/i915/intel_pm.c

5066

PLANE_NV12_BUF_CFG(pipe, plane_id),

sys/dev/drm/i915/intel_pm.c

5067

&ddb->plane[pipe][plane_id]);

sys/dev/drm/i915/intel_pm.c

5069

skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),

sys/dev/drm/i915/intel_pm.c

5070

&ddb->plane[pipe][plane_id]);

sys/dev/drm/i915/intel_pm.c

5071

I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);

sys/dev/drm/i915/intel_pm.c

5181

enum plane_id plane_id = to_intel_plane(plane)->id;

sys/dev/drm/i915/intel_pm.c

5183

if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],

sys/dev/drm/i915/intel_pm.c

5184

&new_ddb->plane[pipe][plane_id]) &&

sys/dev/drm/i915/intel_pm.c

5185

skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],

sys/dev/drm/i915/intel_pm.c

5186

&new_ddb->uv_plane[pipe][plane_id]))

sys/dev/drm/i915/intel_pm.c

5241

enum plane_id plane_id = intel_plane->id;

sys/dev/drm/i915/intel_pm.c

5244

old = &old_ddb->plane[pipe][plane_id];

sys/dev/drm/i915/intel_pm.c

5245

new = &new_ddb->plane[pipe][plane_id];

sys/dev/drm/i915/intel_pm.c

5416

enum plane_id plane_id;

sys/dev/drm/i915/intel_pm.c

5423

for_each_plane_id_on_crtc(crtc, plane_id) {

sys/dev/drm/i915/intel_pm.c

5424

if (plane_id != PLANE_CURSOR)

sys/dev/drm/i915/intel_pm.c

5425

skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],

sys/dev/drm/i915/intel_pm.c

5426

ddb, plane_id);

sys/dev/drm/i915/intel_pm.c

5428

skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],

sys/dev/drm/i915/intel_pm.c

5552

enum plane_id plane_id;

sys/dev/drm/i915/intel_pm.c

5557

for_each_plane_id_on_crtc(intel_crtc, plane_id) {

sys/dev/drm/i915/intel_pm.c

5558

struct skl_plane_wm *wm = &out->planes[plane_id];

sys/dev/drm/i915/intel_pm.c

5561

if (plane_id != PLANE_CURSOR)

sys/dev/drm/i915/intel_pm.c

5562

val = I915_READ(PLANE_WM(pipe, plane_id, level));

sys/dev/drm/i915/intel_pm.c

5569

if (plane_id != PLANE_CURSOR)

sys/dev/drm/i915/intel_pm.c

5570

val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));

sys/dev/drm/i915/intel_pm.c

5791

enum plane_id plane_id;

sys/dev/drm/i915/intel_pm.c

5801

for_each_plane_id_on_crtc(crtc, plane_id) {

sys/dev/drm/i915/intel_pm.c

5802

active->wm.plane[plane_id] =

sys/dev/drm/i915/intel_pm.c

5803

wm->pipe[pipe].plane[plane_id];

sys/dev/drm/i915/intel_pm.c

5815

for_each_plane_id_on_crtc(crtc, plane_id)

sys/dev/drm/i915/intel_pm.c

5816

raw->plane[plane_id] = active->wm.plane[plane_id];

sys/dev/drm/i915/intel_pm.c

5837

for_each_plane_id_on_crtc(crtc, plane_id)

sys/dev/drm/i915/intel_pm.c

5839

plane_id, USHRT_MAX);

sys/dev/drm/i915/intel_pm.c

5875

enum plane_id plane_id = plane->id;

sys/dev/drm/i915/intel_pm.c

5885

raw->plane[plane_id] = 0;

sys/dev/drm/i915/intel_pm.c

5886

wm_state->wm.plane[plane_id] = 0;

sys/dev/drm/i915/intel_pm.c

5889

if (plane_id == PLANE_PRIMARY) {

sys/dev/drm/i915/intel_pm.c

5969

enum plane_id plane_id;

sys/dev/drm/i915/intel_pm.c

5984

for_each_plane_id_on_crtc(crtc, plane_id) {

sys/dev/drm/i915/intel_pm.c

5985

active->wm[level].plane[plane_id] =

sys/dev/drm/i915/intel_pm.c

5986

wm->pipe[pipe].plane[plane_id];

sys/dev/drm/i915/intel_pm.c

5988

raw->plane[plane_id] =

sys/dev/drm/i915/intel_pm.c

5989

vlv_invert_wm_value(active->wm[level].plane[plane_id],

sys/dev/drm/i915/intel_pm.c

5990

fifo_state->plane[plane_id]);

sys/dev/drm/i915/intel_pm.c

5994

for_each_plane_id_on_crtc(crtc, plane_id)

sys/dev/drm/i915/intel_pm.c

5996

plane_id, USHRT_MAX);

sys/dev/drm/i915/intel_pm.c

6031

enum plane_id plane_id = plane->id;

sys/dev/drm/i915/intel_pm.c

6041

raw->plane[plane_id] = 0;

sys/dev/drm/i915/intel_pm.c

6043

wm_state->wm[level].plane[plane_id] =

sys/dev/drm/i915/intel_pm.c

6044

vlv_invert_wm_value(raw->plane[plane_id],

sys/dev/drm/i915/intel_pm.c

6045

fifo_state->plane[plane_id]);

sys/dev/drm/i915/intel_sprite.c

1421

plane = drm_plane_find(dev, file_priv, set->plane_id);

sys/dev/drm/i915/intel_sprite.c

1743

enum i915_pipe pipe, enum plane_id plane_id)

sys/dev/drm/i915/intel_sprite.c

1745

if (plane_id == PLANE_CURSOR)

sys/dev/drm/i915/intel_sprite.c

1755

(plane_id == PLANE_PRIMARY ||

sys/dev/drm/i915/intel_sprite.c

1756

plane_id == PLANE_SPRITE0);

sys/dev/drm/i915/intel_sprite.c

364

enum plane_id plane_id = plane->id;

sys/dev/drm/i915/intel_sprite.c

386

I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

390

I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);

sys/dev/drm/i915/intel_sprite.c

391

I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);

sys/dev/drm/i915/intel_sprite.c

392

I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);

sys/dev/drm/i915/intel_sprite.c

395

I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);

sys/dev/drm/i915/intel_sprite.c

396

I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);

sys/dev/drm/i915/intel_sprite.c

397

I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);

sys/dev/drm/i915/intel_sprite.c

398

I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

400

I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

407

I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);

sys/dev/drm/i915/intel_sprite.c

409

I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);

sys/dev/drm/i915/intel_sprite.c

412

I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);

sys/dev/drm/i915/intel_sprite.c

413

I915_WRITE_FW(PLANE_SURF(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

415

POSTING_READ_FW(PLANE_SURF(pipe, plane_id));

sys/dev/drm/i915/intel_sprite.c

424

enum plane_id plane_id = plane->id;

sys/dev/drm/i915/intel_sprite.c

430

I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);

sys/dev/drm/i915/intel_sprite.c

432

I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);

sys/dev/drm/i915/intel_sprite.c

433

POSTING_READ_FW(PLANE_SURF(pipe, plane_id));

sys/dev/drm/i915/intel_sprite.c

444

enum plane_id plane_id = plane->id;

sys/dev/drm/i915/intel_sprite.c

451

ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;

sys/dev/drm/i915/intel_sprite.c

466

enum plane_id plane_id = plane->id;

sys/dev/drm/i915/intel_sprite.c

497

I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));

sys/dev/drm/i915/intel_sprite.c

498

I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));

sys/dev/drm/i915/intel_sprite.c

499

I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));

sys/dev/drm/i915/intel_sprite.c

501

I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));

sys/dev/drm/i915/intel_sprite.c

502

I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));

sys/dev/drm/i915/intel_sprite.c

503

I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));

sys/dev/drm/i915/intel_sprite.c

504

I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));

sys/dev/drm/i915/intel_sprite.c

505

I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));

sys/dev/drm/i915/intel_sprite.c

507

I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));

sys/dev/drm/i915/intel_sprite.c

508

I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));

sys/dev/drm/i915/intel_sprite.c

509

I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));

sys/dev/drm/i915/intel_sprite.c

511

I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));

sys/dev/drm/i915/intel_sprite.c

512

I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));

sys/dev/drm/i915/intel_sprite.c

513

I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));

sys/dev/drm/i915/intel_sprite.c

526

enum plane_id plane_id = plane->id;

sys/dev/drm/i915/intel_sprite.c

552

I915_WRITE_FW(SPCLRC0(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

554

I915_WRITE_FW(SPCLRC1(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

633

enum plane_id plane_id = plane->id;

sys/dev/drm/i915/intel_sprite.c

660

I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);

sys/dev/drm/i915/intel_sprite.c

661

I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);

sys/dev/drm/i915/intel_sprite.c

662

I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);

sys/dev/drm/i915/intel_sprite.c

664

I915_WRITE_FW(SPSTRIDE(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

666

I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);

sys/dev/drm/i915/intel_sprite.c

669

I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);

sys/dev/drm/i915/intel_sprite.c

671

I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);

sys/dev/drm/i915/intel_sprite.c

673

I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);

sys/dev/drm/i915/intel_sprite.c

675

I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);

sys/dev/drm/i915/intel_sprite.c

676

I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);

sys/dev/drm/i915/intel_sprite.c

677

I915_WRITE_FW(SPSURF(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

679

POSTING_READ_FW(SPSURF(pipe, plane_id));

sys/dev/drm/i915/intel_sprite.c

689

enum plane_id plane_id = plane->id;

sys/dev/drm/i915/intel_sprite.c

694

I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);

sys/dev/drm/i915/intel_sprite.c

696

I915_WRITE_FW(SPSURF(pipe, plane_id), 0);

sys/dev/drm/i915/intel_sprite.c

697

POSTING_READ_FW(SPSURF(pipe, plane_id));

sys/dev/drm/i915/intel_sprite.c

708

enum plane_id plane_id = plane->id;

sys/dev/drm/i915/intel_sprite.c

715

ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;

sys/dev/drm/include/uapi/drm/drm_mode.h

268

__u32 plane_id;

sys/dev/drm/include/uapi/drm/drm_mode.h

287

__u32 plane_id;

sys/dev/drm/include/uapi/drm/i915_drm.h

1391

__u32 plane_id;