bin/cpdup/hclink.c

26

if (pipe(fdin) < 0)

bin/cpdup/hclink.c

28

if (pipe(fdout) < 0) {

bin/pax/ar_io.c

1245

if (pipe(fds) < 0)

bin/sh/eval.c

587

if (pipe(pip) < 0) {

bin/sh/eval.c

689

if (pipe(pip) < 0)

bin/sh/eval.c

991

if (pipe(pip) < 0)

bin/sh/redir.c

275

if (pipe(pip) < 0)

crypto/libressl/apps/openssl/speed.c

2054

if (pipe(fd) == -1) {

crypto/openssh/misc.c

2794

if (pipe(p) == -1) {

crypto/openssh/monitor.c

1816

if (pipe(pair) == -1)

crypto/openssh/readpass.c

64

if (pipe(p) == -1) {

crypto/openssh/scp.c

300

if (pipe(pin) == -1 || pipe(pout) == -1)

crypto/openssh/session.c

409

if (pipe(pin) == -1) {

crypto/openssh/session.c

413

if (pipe(pout) == -1) {

crypto/openssh/session.c

419

if (pipe(perr) == -1) {

crypto/openssh/sftp.c

2369

if ((pipe(pin) == -1) || (pipe(pout) == -1))

crypto/openssh/sshconnect.c

208

if (pipe(pin) == -1 || pipe(pout) == -1)

crypto/openssh/sshconnect2.c

2032

if (pipe(to) == -1) {

crypto/openssh/sshconnect2.c

2036

if (pipe(from) == -1) {

crypto/openssh/sshd.c

1010

if (pipe(startup_p) == -1) {

games/sail/dr_main.c

138

if (pipe(fds)) {

include/unistd.h

408

int pipe(int *);

lib/libdmsg/msg.c

143

if (pipe(iocom->wakeupfds) < 0)

lib/libusb/libusb10.c

171

ret = pipe(ctx->ctrl_pipe);

libexec/fingerd/fingerd.c

164

if (pipe(p) < 0)

libexec/ftpd/popen.c

82

if (pipe(pdes) < 0)

sbin/dhclient/dhclient.c

451

if (pipe(pipe_fd) == -1)

sbin/hammer/cmd_mirror.c

1103

if (pipe(fds) < 0) {

sbin/hammer2/cmd_service.c

443

} else if (pipe(conf->pipefd) < 0) {

sbin/hammer2/cmd_service.c

652

if (pipe(ac->pipefd) == 0) {

sbin/hammer2/cmd_service.c

816

if (pipe(pipefds) < 0) {

sbin/hammer2/cmd_service.c

891

if (pipe(pipefds) < 0) {

sbin/hammer2/cmd_service.c

966

if (pipe(pipefds) < 0) {

sbin/ip6fw/ip6fw.c

1329

if (pipe(pipedes) == -1)

sbin/ipfw/ipfw2.c

2039

struct dn_ioc_pipe pipe;

sbin/ipfw/ipfw2.c

2044

memset(&pipe, 0, sizeof pipe);

sbin/ipfw/ipfw2.c

2057

pipe.pipe_nr = i;

sbin/ipfw/ipfw2.c

2059

pipe.fs.fs_nr = i;

sbin/ipfw/ipfw2.c

2061

&pipe, sizeof pipe);

sbin/ipfw/ipfw2.c

2065

do_pipe == 1 ? pipe.pipe_nr :

sbin/ipfw/ipfw2.c

2066

pipe.fs.fs_nr);

sbin/ipfw/ipfw2.c

2157

struct dn_ioc_pipe pipe;

sbin/ipfw/ipfw2.c

2162

memset(&pipe, 0, sizeof pipe);

sbin/ipfw/ipfw2.c

2169

pipe.pipe_nr = i;

sbin/ipfw/ipfw2.c

2171

pipe.fs.fs_nr = i;

sbin/ipfw/ipfw2.c

2180

pipe.fs.flags_fs |= DN_NOERROR;

sbin/ipfw/ipfw2.c

2190

pipe.fs.plr = (int)(d*0x7fffffff);

sbin/ipfw/ipfw2.c

2197

pipe.fs.qsize = getbw(av[0], &pipe.fs.flags_fs, 1024);

sbin/ipfw/ipfw2.c

2203

pipe.fs.rq_size = strtoul(av[0], NULL, 0);

sbin/ipfw/ipfw2.c

2214

pipe.fs.flow_mask.type = ETHERTYPE_IP;

sbin/ipfw/ipfw2.c

2215

pipe.fs.flow_mask.u.ip.dst_ip = 0;

sbin/ipfw/ipfw2.c

2216

pipe.fs.flow_mask.u.ip.src_ip = 0;

sbin/ipfw/ipfw2.c

2217

pipe.fs.flow_mask.u.ip.dst_port = 0;

sbin/ipfw/ipfw2.c

2218

pipe.fs.flow_mask.u.ip.src_port = 0;

sbin/ipfw/ipfw2.c

2219

pipe.fs.flow_mask.u.ip.proto = 0;

sbin/ipfw/ipfw2.c

2233

pipe.fs.flow_mask.u.ip.dst_ip = ~0;

sbin/ipfw/ipfw2.c

2234

pipe.fs.flow_mask.u.ip.src_ip = ~0;

sbin/ipfw/ipfw2.c

2235

pipe.fs.flow_mask.u.ip.dst_port = ~0;

sbin/ipfw/ipfw2.c

2236

pipe.fs.flow_mask.u.ip.src_port = ~0;

sbin/ipfw/ipfw2.c

2237

pipe.fs.flow_mask.u.ip.proto = ~0;

sbin/ipfw/ipfw2.c

2238

pipe.fs.flags_fs |= DN_HAVE_FLOW_MASK;

sbin/ipfw/ipfw2.c

2242

p32 = &pipe.fs.flow_mask.u.ip.dst_ip;

sbin/ipfw/ipfw2.c

2246

p32 = &pipe.fs.flow_mask.u.ip.src_ip;

sbin/ipfw/ipfw2.c

2250

p16 = &pipe.fs.flow_mask.u.ip.dst_port;

sbin/ipfw/ipfw2.c

2254

p16 = &pipe.fs.flow_mask.u.ip.src_port;

sbin/ipfw/ipfw2.c

2282

pipe.fs.flow_mask.u.ip.proto = (uint8_t)a;

sbin/ipfw/ipfw2.c

2285

pipe.fs.flags_fs |= DN_HAVE_FLOW_MASK;

sbin/ipfw/ipfw2.c

2294

pipe.fs.flags_fs |= DN_IS_RED;

sbin/ipfw/ipfw2.c

2296

pipe.fs.flags_fs |= DN_IS_GENTLE_RED;

sbin/ipfw/ipfw2.c

2304

pipe.fs.w_q = (int) (w_q * (1 << SCALE_RED));

sbin/ipfw/ipfw2.c

2307

pipe.fs.min_th = strtoul(end, &end, 0);

sbin/ipfw/ipfw2.c

2309

pipe.fs.min_th *= 1024;

sbin/ipfw/ipfw2.c

2312

pipe.fs.max_th = strtoul(end, &end, 0);

sbin/ipfw/ipfw2.c

2314

pipe.fs.max_th *= 1024;

sbin/ipfw/ipfw2.c

2320

pipe.fs.max_p = (int)(max_p * (1 << SCALE_RED));

sbin/ipfw/ipfw2.c

2326

pipe.fs.flags_fs &= ~(DN_IS_RED|DN_IS_GENTLE_RED);

sbin/ipfw/ipfw2.c

2336

pipe.bandwidth = getbw(av[0], NULL, 1000);

sbin/ipfw/ipfw2.c

2337

if (pipe.bandwidth < 0)

sbin/ipfw/ipfw2.c

2346

pipe.delay = strtoul(av[0], NULL, 0);

sbin/ipfw/ipfw2.c

2354

pipe.fs.weight = strtoul(av[0], &end, 0);

sbin/ipfw/ipfw2.c

2362

pipe.fs.parent_nr = strtoul(av[0], &end, 0);

sbin/ipfw/ipfw2.c

2371

if (pipe.pipe_nr == 0)

sbin/ipfw/ipfw2.c

2373

if (pipe.delay > 10000)

sbin/ipfw/ipfw2.c

2376

if (pipe.fs.parent_nr == 0)

sbin/ipfw/ipfw2.c

2378

if (pipe.fs.weight >100)

sbin/ipfw/ipfw2.c

2381

if (pipe.fs.flags_fs & DN_QSIZE_IS_BYTES) {

sbin/ipfw/ipfw2.c

2382

if (pipe.fs.qsize > 1024*1024)

sbin/ipfw/ipfw2.c

2385

if (pipe.fs.qsize > 100)

sbin/ipfw/ipfw2.c

2388

if (pipe.fs.flags_fs & DN_IS_RED) {

sbin/ipfw/ipfw2.c

2395

if (pipe.fs.min_th >= pipe.fs.max_th)

sbin/ipfw/ipfw2.c

2397

pipe.fs.min_th, pipe.fs.max_th);

sbin/ipfw/ipfw2.c

2398

if (pipe.fs.max_th == 0)

sbin/ipfw/ipfw2.c

2438

if (pipe.bandwidth==0) /* this is a WF2Q+ queue */

sbin/ipfw/ipfw2.c

2441

step = clock_hz * avg_pkt_size * 8 / pipe.bandwidth;

sbin/ipfw/ipfw2.c

2448

w_q = ((double)pipe.fs.w_q) / (1 << SCALE_RED);

sbin/ipfw/ipfw2.c

2450

pipe.fs.lookup_step = (int)idle / lookup_depth;

sbin/ipfw/ipfw2.c

2451

if (!pipe.fs.lookup_step)

sbin/ipfw/ipfw2.c

2452

pipe.fs.lookup_step = 1;

sbin/ipfw/ipfw2.c

2454

for (t = pipe.fs.lookup_step; t > 0; --t)

sbin/ipfw/ipfw2.c

2456

pipe.fs.lookup_weight = (int)(weight * (1 << SCALE_RED));

sbin/ipfw/ipfw2.c

2458

i = setsockopt(s, IPPROTO_IP, IP_DUMMYNET_CONFIGURE, &pipe,

sbin/ipfw/ipfw2.c

2459

sizeof pipe);

sbin/ipfw/ipfw2.c

4202

if (pipe(pipedes) == -1)

sbin/ipfw3/ipfw3.c

1151

if (pipe(pipedes) == -1)

sbin/ipfw3/ipfw3dummynet.c

155

struct dn_ioc_pipe pipe;

sbin/ipfw3/ipfw3dummynet.c

162

memset(&pipe, 0, sizeof pipe);

sbin/ipfw3/ipfw3dummynet.c

168

pipe.pipe_nr = i;

sbin/ipfw3/ipfw3dummynet.c

170

pipe.fs.fs_nr = i;

sbin/ipfw3/ipfw3dummynet.c

181

pipe.fs.flags_fs |= DN_NOERROR;

sbin/ipfw3/ipfw3dummynet.c

191

pipe.fs.plr = (int)(d*0x7fffffff);

sbin/ipfw3/ipfw3dummynet.c

198

pipe.fs.qsize = getbw(av[0], &pipe.fs.flags_fs, 1024);

sbin/ipfw3/ipfw3dummynet.c

204

pipe.fs.rq_size = strtoul(av[0], NULL, 0);

sbin/ipfw3/ipfw3dummynet.c

216

pipe.fs.flow_mask.type = ETHERTYPE_IP;

sbin/ipfw3/ipfw3dummynet.c

217

pipe.fs.flow_mask.u.ip.dst_ip = 0;

sbin/ipfw3/ipfw3dummynet.c

218

pipe.fs.flow_mask.u.ip.src_ip = 0;

sbin/ipfw3/ipfw3dummynet.c

219

pipe.fs.flow_mask.u.ip.dst_port = 0;

sbin/ipfw3/ipfw3dummynet.c

220

pipe.fs.flow_mask.u.ip.src_port = 0;

sbin/ipfw3/ipfw3dummynet.c

221

pipe.fs.flow_mask.u.ip.proto = 0;

sbin/ipfw3/ipfw3dummynet.c

235

pipe.fs.flow_mask.u.ip.dst_ip = ~0;

sbin/ipfw3/ipfw3dummynet.c

236

pipe.fs.flow_mask.u.ip.src_ip = ~0;

sbin/ipfw3/ipfw3dummynet.c

237

pipe.fs.flow_mask.u.ip.dst_port = ~0;

sbin/ipfw3/ipfw3dummynet.c

238

pipe.fs.flow_mask.u.ip.src_port = ~0;

sbin/ipfw3/ipfw3dummynet.c

239

pipe.fs.flow_mask.u.ip.proto = ~0;

sbin/ipfw3/ipfw3dummynet.c

240

pipe.fs.flags_fs |= DN_HAVE_FLOW_MASK;

sbin/ipfw3/ipfw3dummynet.c

244

p32 = &pipe.fs.flow_mask.u.ip.dst_ip;

sbin/ipfw3/ipfw3dummynet.c

248

p32 = &pipe.fs.flow_mask.u.ip.src_ip;

sbin/ipfw3/ipfw3dummynet.c

252

p16 = &pipe.fs.flow_mask.u.ip.dst_port;

sbin/ipfw3/ipfw3dummynet.c

256

p16 = &pipe.fs.flow_mask.u.ip.src_port;

sbin/ipfw3/ipfw3dummynet.c

284

pipe.fs.flow_mask.u.ip.proto =

sbin/ipfw3/ipfw3dummynet.c

288

pipe.fs.flags_fs |= DN_HAVE_FLOW_MASK;

sbin/ipfw3/ipfw3dummynet.c

298

pipe.fs.flags_fs |= DN_IS_RED;

sbin/ipfw3/ipfw3dummynet.c

300

pipe.fs.flags_fs |= DN_IS_GENTLE_RED;

sbin/ipfw3/ipfw3dummynet.c

308

pipe.fs.w_q = (int) (w_q * (1 << SCALE_RED));

sbin/ipfw3/ipfw3dummynet.c

311

pipe.fs.min_th = strtoul(end, &end, 0);

sbin/ipfw3/ipfw3dummynet.c

313

pipe.fs.min_th *= 1024;

sbin/ipfw3/ipfw3dummynet.c

316

pipe.fs.max_th = strtoul(end, &end, 0);

sbin/ipfw3/ipfw3dummynet.c

318

pipe.fs.max_th *= 1024;

sbin/ipfw3/ipfw3dummynet.c

324

pipe.fs.max_p = (int)(max_p * (1 << SCALE_RED));

sbin/ipfw3/ipfw3dummynet.c

330

pipe.fs.flags_fs &= ~(DN_IS_RED|DN_IS_GENTLE_RED);

sbin/ipfw3/ipfw3dummynet.c

341

pipe.bandwidth = getbw(av[0], NULL, 1000);

sbin/ipfw3/ipfw3dummynet.c

342

if (pipe.bandwidth < 0)

sbin/ipfw3/ipfw3dummynet.c

351

pipe.delay = strtoul(av[0], NULL, 0);

sbin/ipfw3/ipfw3dummynet.c

360

pipe.fs.weight = strtoul(av[0], &end, 0);

sbin/ipfw3/ipfw3dummynet.c

368

pipe.fs.parent_nr = strtoul(av[0], &end, 0);

sbin/ipfw3/ipfw3dummynet.c

377

if (pipe.pipe_nr == 0)

sbin/ipfw3/ipfw3dummynet.c

379

if (pipe.delay > 10000)

sbin/ipfw3/ipfw3dummynet.c

382

if (pipe.fs.parent_nr == 0)

sbin/ipfw3/ipfw3dummynet.c

384

if (pipe.fs.weight >100)

sbin/ipfw3/ipfw3dummynet.c

387

if (pipe.fs.flags_fs & DN_QSIZE_IS_BYTES) {

sbin/ipfw3/ipfw3dummynet.c

388

if (pipe.fs.qsize > 1024*1024)

sbin/ipfw3/ipfw3dummynet.c

391

if (pipe.fs.qsize > 100)

sbin/ipfw3/ipfw3dummynet.c

394

if (pipe.fs.flags_fs & DN_IS_RED) {

sbin/ipfw3/ipfw3dummynet.c

401

if (pipe.fs.min_th >= pipe.fs.max_th)

sbin/ipfw3/ipfw3dummynet.c

403

pipe.fs.min_th, pipe.fs.max_th);

sbin/ipfw3/ipfw3dummynet.c

404

if (pipe.fs.max_th == 0)

sbin/ipfw3/ipfw3dummynet.c

444

if (pipe.bandwidth == 0) /* this is a WF2Q+ queue */

sbin/ipfw3/ipfw3dummynet.c

447

s = clock_hz * avg_pkt_size * 8 / pipe.bandwidth;

sbin/ipfw3/ipfw3dummynet.c

454

w_q = ((double)pipe.fs.w_q) / (1 << SCALE_RED);

sbin/ipfw3/ipfw3dummynet.c

456

pipe.fs.lookup_step = (int)idle / lookup_depth;

sbin/ipfw3/ipfw3dummynet.c

457

if (!pipe.fs.lookup_step)

sbin/ipfw3/ipfw3dummynet.c

458

pipe.fs.lookup_step = 1;

sbin/ipfw3/ipfw3dummynet.c

460

for (t = pipe.fs.lookup_step; t > 0; --t)

sbin/ipfw3/ipfw3dummynet.c

462

pipe.fs.lookup_weight = (int)(weight * (1 << SCALE_RED));

sbin/ipfw3/ipfw3dummynet.c

464

i = do_set_x(IP_DUMMYNET_CONFIGURE, &pipe, sizeof pipe);

sbin/svc/execute.c

103

if (pipe(fds) < 0) {

sbin/svc/execute.c

213

pipe(cmd->logfds);

sys/dev/drm/amd/amdgpu/amdgpu.h

1242

u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/amd/amdgpu/amdgpu.h

1243

int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/amd/amdgpu/amdgpu.h

1244

void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.c

150

adev->gfx.kiq.ring.pipe,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

193

static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

197

uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

217

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

219

lock_srbm(kgd, mec, pipe, queue_id, 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

276

uint32_t pipe;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

279

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

281

lock_srbm(kgd, mec, pipe, 0, 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

329

uint32_t value, mec, pipe;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

332

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

335

mec, pipe, queue_id);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

338

((mec << 5) | (pipe << 3) | queue_id | 0x80));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

232

static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

238

soc15_grbm_select(adev, mec, pipe, queue, vmid);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

255

uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

257

lock_srbm(kgd, mec, pipe, queue_id, 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

356

uint32_t pipe;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

359

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

361

lock_srbm(kgd, mec, pipe, 0, 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

418

uint32_t value, mec, pipe;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

421

pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

424

mec, pipe, queue_id);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

427

((mec << 5) | (pipe << 3) | queue_id | 0x80));

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

106

unsigned instance_bank, sh_bank, se_bank, me, pipe, queue;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

109

instance_bank = sh_bank = se_bank = me = pipe = queue = 0;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

133

pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

152

amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue);

sys/dev/drm/amd/amdgpu/amdgpu_display.c

775

unsigned int pipe, unsigned int flags, int *vpos,

sys/dev/drm/amd/amdgpu/amdgpu_display.c

791

if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)

sys/dev/drm/amd/amdgpu/amdgpu_display.c

834

vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;

sys/dev/drm/amd/amdgpu/amdgpu_drv.c

1292

amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,

sys/dev/drm/amd/amdgpu/amdgpu_drv.c

1297

return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

165

int i, queue, pipe, mec;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

171

pipe = (i / adev->gfx.mec.num_queue_per_pipe)

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

186

if (mec == 0 && pipe == 0)

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

205

int mec, pipe, queue;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

215

amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue);

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

222

if ((mec == 1 && pipe > 1) || queue != 0)

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

226

ring->pipe = pipe;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

259

ksprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

37

int pipe, int queue)

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

43

bit += pipe * adev->gfx.mec.num_queue_per_pipe;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

50

int *mec, int *pipe, int *queue)

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

53

*pipe = (bit / adev->gfx.mec.num_queue_per_pipe)

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

61

int mec, int pipe, int queue)

sys/dev/drm/amd/amdgpu/amdgpu_gfx.c

63

return test_bit(amdgpu_gfx_queue_to_bit(adev, mec, pipe, queue),

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

214

void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

316

#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q))

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

354

int pipe, int queue);

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

356

int *mec, int *pipe, int *queue);

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

358

int pipe, int queue);

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1105

u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1111

if (pipe >= adev->mode_info.num_crtc) {

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1112

DRM_ERROR("Invalid crtc %u\n", pipe);

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1124

if (adev->mode_info.crtcs[pipe]) {

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1129

count = amdgpu_display_vblank_get_counter(adev, pipe);

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1135

dev, pipe, GET_DISTANCE_TO_VBLANKSTART,

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1137

&adev->mode_info.crtcs[pipe]->base.hwmode);

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1138

} while (count != amdgpu_display_vblank_get_counter(adev, pipe));

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1145

pipe, vpos);

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1156

count = amdgpu_display_vblank_get_counter(adev, pipe);

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1172

int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1175

int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1188

void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

1191

int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

607

unsigned int pipe, unsigned int flags, int *vpos,

sys/dev/drm/amd/amdgpu/amdgpu_ring.h

195

u32 pipe;

sys/dev/drm/amd/amdgpu/cik.c

868

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/drm/amd/amdgpu/cik.c

871

(((pipe << SRBM_GFX_CNTL__PIPEID__SHIFT) & SRBM_GFX_CNTL__PIPEID_MASK)|

sys/dev/drm/amd/amdgpu/cik.h

30

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2116

ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2119

ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2843

int mec, int pipe)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2847

size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2853

cik_srbm_select(adev, mec + 1, pipe, 0, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3058

cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4278

u32 me, u32 pipe, u32 q)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4280

cik_srbm_select(adev, me, pipe, q, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4468

int mec, int pipe, int queue)

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4476

ring->pipe = pipe;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4482

sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4486

+ ring->pipe;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4797

int me, int pipe,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4809

switch (pipe) {

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4823

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4955

if ((ring->me == me_id) && (ring->pipe == pipe_id))

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1985

int mec, int pipe, int queue)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1995

ring->pipe = pipe;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2003

ksprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2007

+ ring->pipe;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3545

u32 me, u32 pipe, u32 q)

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3547

vi_srbm_select(adev, me, pipe, q, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4414

tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4468

PACKET3_MAP_QUEUES_PIPE(ring->pipe) |

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4704

vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4713

vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4737

vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5093

vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5189

vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6099

ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6102

ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6266

pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6282

int i, pipe;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6287

pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6289

set_bit(pipe, adev->gfx.pipe_reserve_bitmap);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6291

clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6306

pipe = amdgpu_gfx_queue_to_bit(adev,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6308

iring->pipe,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6310

reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6316

pipe = amdgpu_gfx_queue_to_bit(adev,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6318

iring->pipe,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6320

reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6336

vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6529

int me, int pipe,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6541

switch (pipe) {

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6555

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6735

if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1373

u32 me, u32 pipe, u32 q)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1375

soc15_grbm_select(adev, me, pipe, q, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1668

int mec, int pipe, int queue)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1678

ring->pipe = pipe;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1686

sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1690

+ ring->pipe;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2804

tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2858

PACKET3_MAP_QUEUES_PIPE(ring->pipe) |

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3180

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3189

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3213

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3430

adev->gfx.kiq.ring.pipe,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4056

ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4059

ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4206

pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4222

int i, pipe;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4227

pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4229

set_bit(pipe, adev->gfx.pipe_reserve_bitmap);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4231

clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4246

pipe = amdgpu_gfx_queue_to_bit(adev,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4248

iring->pipe,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4250

reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4256

pipe = amdgpu_gfx_queue_to_bit(adev,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4258

iring->pipe,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4260

reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4276

soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4540

int me, int pipe,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4552

switch (pipe) {

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4566

DRM_DEBUG("invalid pipe %d\n", pipe);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4692

if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))

sys/dev/drm/amd/amdgpu/si_dpm.c

4148

u32 tmp, pipe;

sys/dev/drm/amd/amdgpu/si_dpm.c

4165

pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;

sys/dev/drm/amd/amdgpu/si_dpm.c

4168

(!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {

sys/dev/drm/amd/amdgpu/si_dpm.c

4175

pipe = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

4177

pipe = i;

sys/dev/drm/amd/amdgpu/si_dpm.c

4180

tmp |= DCCG_DISP1_SLOW_SELECT(pipe);

sys/dev/drm/amd/amdgpu/soc15.c

220

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/drm/amd/amdgpu/soc15.c

223

grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/drm/amd/amdgpu/soc15.h

51

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/drm/amd/amdgpu/vi.c

359

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/drm/amd/amdgpu/vi.c

362

srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);

sys/dev/drm/amd/amdgpu/vi.h

30

u32 me, u32 pipe, u32 queue, u32 vmid);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2757

const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data)

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2774

if (!pipe[i].stream || !pipe[i].bottom_pipe)

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2777

ASSERT(pipe[i].plane_state);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2780

if (!pipe[i].plane_state->visible)

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2785

if (!pipe[i].plane_state->visible)

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2793

data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2794

data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2795

data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2796

data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2798

data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2799

data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2800

data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2801

data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2802

data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2803

switch (pipe[i].plane_state->rotation) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2819

switch (pipe[i].plane_state->format) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2850

data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2851

data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2853

pipe[i].bottom_pipe->plane_state->plane_size.grph.surface_pitch);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2854

data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2855

data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2857

pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2859

pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2860

switch (pipe[i].bottom_pipe->plane_state->rotation) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2885

if (!pipe[i].stream || pipe[i].bottom_pipe)

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2891

data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2892

data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2893

pixel_clock_khz = pipe[i].stream->timing.pix_clk_khz;

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2894

if (pipe[i].stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2897

if (pipe[i].plane_state) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2898

data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2900

data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2901

data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2902

data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2903

data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2904

data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2905

switch (pipe[i].plane_state->rotation) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2921

switch (pipe[i].plane_state->format) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2945

} else if (pipe[i].stream->dst.width != 0 &&

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2946

pipe[i].stream->dst.height != 0 &&

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2947

pipe[i].stream->src.width != 0 &&

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2948

pipe[i].stream->src.height != 0) {

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2949

data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.width);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2951

data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.height);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2952

data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_to_fixed(1) : bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2953

data->v_taps[num_displays + 4] = pipe[i].stream->src.height == pipe[i].stream->dst.height ? bw_int_to_fixed(1) : bw_int_to_fixed(2);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2954

data->h_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.width, pipe[i].stream->dst.width);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2955

data->v_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.height, pipe[i].stream->dst.height);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2959

data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2961

data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2988

const struct pipe_ctx pipe[],

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2997

populate_initial_data(pipe, pipe_count, data);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1090

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1093

if (!pipe->stream)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1096

if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1099

pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1100

pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1101

pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1102

pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1104

pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1105

pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1106

vesa_sync_start = pipe->stream->timing.v_addressable +

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1107

pipe->stream->timing.v_border_bottom +

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1108

pipe->stream->timing.v_front_porch;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1110

asic_blank_end = (pipe->stream->timing.v_total -

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1112

pipe->stream->timing.v_border_top)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1113

* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1116

(pipe->stream->timing.v_border_top +

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1117

pipe->stream->timing.v_addressable +

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1118

pipe->stream->timing.v_border_bottom)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1119

* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1121

pipe->pipe_dlg_param.vblank_start = asic_blank_start;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1122

pipe->pipe_dlg_param.vblank_end = asic_blank_end;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1124

if (pipe->plane_state) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1125

struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1127

pipe->plane_state->update_flags.bits.full_update = 1;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1130

((pipe->stream->view_format ==

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1132

pipe->stream->view_format ==

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1134

(pipe->stream->timing.timing_3d_format ==

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1136

pipe->stream->timing.timing_3d_format ==

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1138

if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1145

hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1146

hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1147

hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1148

hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1155

pipe, hsplit_pipe);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1159

} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1161

pipe->bottom_pipe = hsplit_pipe->bottom_pipe;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1163

hsplit_pipe->bottom_pipe->top_pipe = pipe;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1171

resource_build_scaling_params(pipe);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1174

dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

251

const struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

255

if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

257

else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

260

if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

265

input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

275

input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

276

dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

279

input->src.meta_pitch = pipe->plane_state->dcc.grph.meta_pitch;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

281

input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

283

input->src.viewport_width = pipe->plane_res.scl_data.viewport.width;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

284

input->src.viewport_height = pipe->plane_res.scl_data.viewport.height;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

285

input->src.data_pitch = pipe->plane_res.scl_data.viewport.width;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

286

input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

290

switch (pipe->plane_state->tiling_info.gfx9.swizzle) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

338

switch (pipe->plane_state->rotation) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

353

switch (pipe->plane_state->format) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

380

input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

381

input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

382

input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

383

input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

386

input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

387

input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

388

input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

389

input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

390

input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

391

input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

394

switch (pipe->plane_res.scl_data.lb_params.depth) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

404

input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

405

+ pipe->stream->timing.v_border_bottom;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

407

input->dest.recout_width = pipe->plane_res.scl_data.recout.width;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

408

input->dest.recout_height = pipe->plane_res.scl_data.recout.height;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

410

input->dest.full_recout_width = pipe->plane_res.scl_data.recout.width;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

411

input->dest.full_recout_height = pipe->plane_res.scl_data.recout.height;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

413

input->dest.htotal = pipe->stream->timing.h_total;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

414

input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

416

- pipe->stream->timing.h_addressable

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

417

- pipe->stream->timing.h_border_left

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

418

- pipe->stream->timing.h_border_right;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

420

input->dest.vtotal = pipe->stream->timing.v_total;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

421

input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

423

- pipe->stream->timing.v_addressable

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

424

- pipe->stream->timing.v_border_bottom

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

425

- pipe->stream->timing.v_border_top;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

426

input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

427

input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

428

input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

429

input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

430

input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

437

struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

441

struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

442

struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

443

struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

472

pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

487

dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

499

pipe->plane_state->flip_immediate);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

837

struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

839

if (!pipe->stream)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

842

if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

848

v->htotal[input_idx] = pipe->stream->timing.h_total;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

849

v->vtotal[input_idx] = pipe->stream->timing.v_total;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

850

v->vactive[input_idx] = pipe->stream->timing.v_addressable +

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

851

pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

852

v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

854

- pipe->stream->timing.v_front_porch;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

855

v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz/1000.0;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

856

if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

858

if (!pipe->plane_state) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

863

v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

864

v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

865

v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

866

v->scaler_recout_height[input_idx] = pipe->stream->timing.v_addressable;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

874

v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

875

v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

876

v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

877

v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

878

if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

879

if (pipe->plane_state->rotation % 2 == 0) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

880

int viewport_end = pipe->plane_res.scl_data.viewport.width

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

881

+ pipe->plane_res.scl_data.viewport.x;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

882

int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

883

+ pipe->bottom_pipe->plane_res.scl_data.viewport.x;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

887

- pipe->bottom_pipe->plane_res.scl_data.viewport.x;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

890

- pipe->plane_res.scl_data.viewport.x;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

892

int viewport_end = pipe->plane_res.scl_data.viewport.height

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

893

+ pipe->plane_res.scl_data.viewport.y;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

894

int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

895

+ pipe->bottom_pipe->plane_res.scl_data.viewport.y;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

899

- pipe->bottom_pipe->plane_res.scl_data.viewport.y;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

902

- pipe->plane_res.scl_data.viewport.y;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

904

v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

905

+ pipe->bottom_pipe->plane_res.scl_data.recout.width;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

908

if (pipe->plane_state->rotation % 2 == 0) {

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

909

ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

911

ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

914

ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

916

ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

925

v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

936

pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

940

pipe->plane_state->format);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

942

pipe->plane_state->tiling_info.gfx9.swizzle);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

943

v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

944

v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

945

v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

946

v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

947

v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

957

v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

962

v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

964

v->output[input_idx] = pipe->stream->sink->sink_signal ==

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

968

switch (pipe->stream->timing.display_color_depth) {

sys/dev/drm/amd/display/dc/core/dc.c

1002

pipe = &context->res_ctx.pipe_ctx[k];

sys/dev/drm/amd/display/dc/core/dc.c

1004

for (l = 0 ; pipe && l < context->stream_count; l++) {

sys/dev/drm/amd/display/dc/core/dc.c

1006

context->streams[l] == pipe->stream &&

sys/dev/drm/amd/display/dc/core/dc.c

1008

dc->hwss.setup_stereo(pipe, dc);

sys/dev/drm/amd/display/dc/core/dc.c

202

struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

204

if (pipe->stream == stream && pipe->stream_res.stream_enc) {

sys/dev/drm/amd/display/dc/core/dc.c

205

pipe->stream->adjust = *adjust;

sys/dev/drm/amd/display/dc/core/dc.c

206

dc->hwss.set_drr(&pipe,

sys/dev/drm/amd/display/dc/core/dc.c

228

struct pipe_ctx *pipe =

sys/dev/drm/amd/display/dc/core/dc.c

231

if (pipe->stream == stream && pipe->stream_res.stream_enc) {

sys/dev/drm/amd/display/dc/core/dc.c

232

dc->hwss.get_position(&pipe, 1, &position);

sys/dev/drm/amd/display/dc/core/dc.c

257

struct pipe_ctx *pipe;

sys/dev/drm/amd/display/dc/core/dc.c

262

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

263

if (pipe->stream == stream)

sys/dev/drm/amd/display/dc/core/dc.c

273

param.windowa_x_end = pipe->stream->timing.h_addressable;

sys/dev/drm/amd/display/dc/core/dc.c

274

param.windowa_y_end = pipe->stream->timing.v_addressable;

sys/dev/drm/amd/display/dc/core/dc.c

277

param.windowb_x_end = pipe->stream->timing.h_addressable;

sys/dev/drm/amd/display/dc/core/dc.c

278

param.windowb_y_end = pipe->stream->timing.v_addressable;

sys/dev/drm/amd/display/dc/core/dc.c

285

tg = pipe->stream_res.tg;

sys/dev/drm/amd/display/dc/core/dc.c

307

struct pipe_ctx *pipe;

sys/dev/drm/amd/display/dc/core/dc.c

311

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

312

if (pipe->stream == stream)

sys/dev/drm/amd/display/dc/core/dc.c

319

tg = pipe->stream_res.tg;

sys/dev/drm/amd/display/dc/core/dc.c

465

struct pipe_ctx *pipe;

sys/dev/drm/amd/display/dc/core/dc.c

470

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

471

if (pipe->stream && pipe->stream->sink

sys/dev/drm/amd/display/dc/core/dc.c

472

&& pipe->stream->sink->link) {

sys/dev/drm/amd/display/dc/core/dc.c

473

if (pipe->stream->sink->link == link)

sys/dev/drm/amd/display/dc/core/dc.c

907

struct pipe_ctx *pipe;

sys/dev/drm/amd/display/dc/core/dc.c

911

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

913

pipe = &dc->current_state->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

914

for (j = 0 ; pipe && j < stream_count; j++) {

sys/dev/drm/amd/display/dc/core/dc.c

915

if (streams[j] && streams[j] == pipe->stream &&

sys/dev/drm/amd/display/dc/core/dc.c

917

dc->hwss.setup_stereo(pipe, dc);

sys/dev/drm/amd/display/dc/core/dc.c

932

struct pipe_ctx *pipe;

sys/dev/drm/amd/display/dc/core/dc.c

967

pipe = &context->res_ctx.pipe_ctx[i];

sys/dev/drm/amd/display/dc/core/dc.c

968

dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);

sys/dev/drm/amd/display/dc/core/dc_resource.c

388

const struct pipe_ctx *pipe)

sys/dev/drm/amd/display/dc/core/dc_resource.c

397

(dc_is_dp_signal(pipe->stream->signal) &&

sys/dev/drm/amd/display/dc/core/dc_resource.c

399

pipe->stream)))

sys/dev/drm/amd/display/dc/core/dc_resource.c

403

&& dc_is_dual_link_signal(pipe->stream->signal))

sys/dev/drm/amd/display/dc/core/dc_resource.c

406

if (dc_is_hdmi_signal(pipe->stream->signal)

sys/dev/drm/amd/display/dc/core/dc_resource.c

411

pipe_with_clk_src->stream, pipe->stream))

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

48

struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

56

if (lock && pipe->stream_res.tg->funcs->is_blanked &&

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

57

pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

60

val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

71

REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

76

REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

82

uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);

sys/dev/drm/amd/display/dc/dce/dce_hwseq.c

83

REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);

sys/dev/drm/amd/display/dc/dce/dce_hwseq.h

531

struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1305

struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1311

if (pipe->top_pipe)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1318

pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1320

pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);

sys/dev/drm/amd/display/dc/dml/display_mode_structs.h

328

display_pipe_params_st pipe;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1182

dcc_en = e2e_pipe_param.pipe.src.dcc;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1184

(enum source_format_class) e2e_pipe_param.pipe.src.source_format);

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1186

access_dir = (e2e_pipe_param.pipe.src.source_scan == dm_vert); /* vp access direction: horizontal or vertical accessed */

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1188

(enum source_format_class) e2e_pipe_param.pipe.src.source_format,

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1191

(enum source_format_class) e2e_pipe_param.pipe.src.source_format,

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1193

vp_height_l = e2e_pipe_param.pipe.src.viewport_height;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1194

vp_width_l = e2e_pipe_param.pipe.src.viewport_width;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1195

vp_height_c = e2e_pipe_param.pipe.src.viewport_height_c;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1196

vp_width_c = e2e_pipe_param.pipe.src.viewport_width_c;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1199

htaps_l = e2e_pipe_param.pipe.scale_taps.htaps;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1200

htaps_c = e2e_pipe_param.pipe.scale_taps.htaps_c;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1201

hratios_l = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1202

hratios_c = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio_c;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1203

vratio_l = e2e_pipe_param.pipe.scale_ratio_depth.vscl_ratio;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1204

vratio_c = e2e_pipe_param.pipe.scale_ratio_depth.vscl_ratio_c;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1207

vinit_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1208

vinit_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_c;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1209

vinit_bot_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1210

vinit_bot_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot_c;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1225

vupdate_offset = e2e_pipe_param.pipe.dest.vupdate_offset;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1226

vupdate_width = e2e_pipe_param.pipe.dest.vupdate_width;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1227

vready_offset = e2e_pipe_param.pipe.dest.vready_offset;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1234

vstartup_start = e2e_pipe_param.pipe.dest.vstartup_start;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1261

if (e2e_pipe_param.pipe.src.is_hsplit)

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1263

+ e2e_pipe_param.pipe.dest.recout_width;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1635

if (e2e_pipe_param.pipe.src.is_hsplit) {

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1636

if (e2e_pipe_param.pipe.dest.full_recout_width == 0) {

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1638

full_recout_width = e2e_pipe_param.pipe.dest.recout_width * 2; /* assume half split for dcn1 */

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1640

full_recout_width = e2e_pipe_param.pipe.dest.full_recout_width;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1642

full_recout_width = e2e_pipe_param.pipe.dest.recout_width;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1809

hratios_cur0 = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1810

cur0_src_width = e2e_pipe_param.pipe.src.cur0_src_width; /* cursor source width */

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1811

cur0_bpp = (enum cursor_bpp) e2e_pipe_param.pipe.src.cur0_bpp;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

992

unsigned int htotal = e2e_pipe_param.pipe.dest.htotal;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

993

unsigned int hblank_end = e2e_pipe_param.pipe.dest.hblank_end;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

994

unsigned int vblank_start = e2e_pipe_param.pipe.dest.vblank_start;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

995

unsigned int vblank_end = e2e_pipe_param.pipe.dest.vblank_end;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

996

bool interlaced = e2e_pipe_param.pipe.dest.interlaced;

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

999

double pclk_freq_in_mhz = e2e_pipe_param.pipe.dest.pixel_rate_mhz;

sys/dev/drm/amd/display/dc/inc/dce_calcs.h

484

const struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

173

struct pipe_ctx *pipe,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

226

void (*set_cursor_position)(struct pipe_ctx *pipe);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

227

void (*set_cursor_attribute)(struct pipe_ctx *pipe);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

228

void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);

sys/dev/drm/drm_gem_framebuffer_helper.c

281

int drm_gem_fb_simple_display_pipe_prepare_fb(struct drm_simple_display_pipe *pipe,

sys/dev/drm/drm_gem_framebuffer_helper.c

284

return drm_gem_fb_prepare_fb(&pipe->plane, plane_state);

sys/dev/drm/drm_internal.h

67

void drm_vblank_disable_and_save(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/drm_simple_kms_helper.c

101

pipe = container_of(crtc, struct drm_simple_display_pipe, crtc);

sys/dev/drm/drm_simple_kms_helper.c

102

if (!pipe->funcs || !pipe->funcs->enable_vblank)

sys/dev/drm/drm_simple_kms_helper.c

105

return pipe->funcs->enable_vblank(pipe);

sys/dev/drm/drm_simple_kms_helper.c

110

struct drm_simple_display_pipe *pipe;

sys/dev/drm/drm_simple_kms_helper.c

112

pipe = container_of(crtc, struct drm_simple_display_pipe, crtc);

sys/dev/drm/drm_simple_kms_helper.c

113

if (!pipe->funcs || !pipe->funcs->disable_vblank)

sys/dev/drm/drm_simple_kms_helper.c

116

pipe->funcs->disable_vblank(pipe);

sys/dev/drm/drm_simple_kms_helper.c

133

struct drm_simple_display_pipe *pipe;

sys/dev/drm/drm_simple_kms_helper.c

137

pipe = container_of(plane, struct drm_simple_display_pipe, plane);

sys/dev/drm/drm_simple_kms_helper.c

139

&pipe->crtc);

sys/dev/drm/drm_simple_kms_helper.c

151

if (!pipe->funcs || !pipe->funcs->check)

sys/dev/drm/drm_simple_kms_helper.c

154

return pipe->funcs->check(pipe, plane_state, crtc_state);

sys/dev/drm/drm_simple_kms_helper.c

160

struct drm_simple_display_pipe *pipe;

sys/dev/drm/drm_simple_kms_helper.c

162

pipe = container_of(plane, struct drm_simple_display_pipe, plane);

sys/dev/drm/drm_simple_kms_helper.c

163

if (!pipe->funcs || !pipe->funcs->update)

sys/dev/drm/drm_simple_kms_helper.c

166

pipe->funcs->update(pipe, old_pstate);

sys/dev/drm/drm_simple_kms_helper.c

172

struct drm_simple_display_pipe *pipe;

sys/dev/drm/drm_simple_kms_helper.c

174

pipe = container_of(plane, struct drm_simple_display_pipe, plane);

sys/dev/drm/drm_simple_kms_helper.c

175

if (!pipe->funcs || !pipe->funcs->prepare_fb)

sys/dev/drm/drm_simple_kms_helper.c

178

return pipe->funcs->prepare_fb(pipe, state);

sys/dev/drm/drm_simple_kms_helper.c

184

struct drm_simple_display_pipe *pipe;

sys/dev/drm/drm_simple_kms_helper.c

186

pipe = container_of(plane, struct drm_simple_display_pipe, plane);

sys/dev/drm/drm_simple_kms_helper.c

187

if (!pipe->funcs || !pipe->funcs->cleanup_fb)

sys/dev/drm/drm_simple_kms_helper.c

190

pipe->funcs->cleanup_fb(pipe, state);

sys/dev/drm/drm_simple_kms_helper.c

223

int drm_simple_display_pipe_attach_bridge(struct drm_simple_display_pipe *pipe,

sys/dev/drm/drm_simple_kms_helper.c

226

return drm_bridge_attach(&pipe->encoder, bridge, NULL);

sys/dev/drm/drm_simple_kms_helper.c

255

struct drm_simple_display_pipe *pipe,

sys/dev/drm/drm_simple_kms_helper.c

261

struct drm_encoder *encoder = &pipe->encoder;

sys/dev/drm/drm_simple_kms_helper.c

262

struct drm_plane *plane = &pipe->plane;

sys/dev/drm/drm_simple_kms_helper.c

263

struct drm_crtc *crtc = &pipe->crtc;

sys/dev/drm/drm_simple_kms_helper.c

266

pipe->connector = connector;

sys/dev/drm/drm_simple_kms_helper.c

267

pipe->funcs = funcs;

sys/dev/drm/drm_simple_kms_helper.c

41

struct drm_simple_display_pipe *pipe;

sys/dev/drm/drm_simple_kms_helper.c

43

pipe = container_of(crtc, struct drm_simple_display_pipe, crtc);

sys/dev/drm/drm_simple_kms_helper.c

44

if (!pipe->funcs || !pipe->funcs->mode_valid)

sys/dev/drm/drm_simple_kms_helper.c

48

return pipe->funcs->mode_valid(crtc, mode);

sys/dev/drm/drm_simple_kms_helper.c

68

struct drm_simple_display_pipe *pipe;

sys/dev/drm/drm_simple_kms_helper.c

70

pipe = container_of(crtc, struct drm_simple_display_pipe, crtc);

sys/dev/drm/drm_simple_kms_helper.c

71

if (!pipe->funcs || !pipe->funcs->enable)

sys/dev/drm/drm_simple_kms_helper.c

74

plane = &pipe->plane;

sys/dev/drm/drm_simple_kms_helper.c

75

pipe->funcs->enable(pipe, crtc->state, plane->state);

sys/dev/drm/drm_simple_kms_helper.c

81

struct drm_simple_display_pipe *pipe;

sys/dev/drm/drm_simple_kms_helper.c

83

pipe = container_of(crtc, struct drm_simple_display_pipe, crtc);

sys/dev/drm/drm_simple_kms_helper.c

84

if (!pipe->funcs || !pipe->funcs->disable)

sys/dev/drm/drm_simple_kms_helper.c

87

pipe->funcs->disable(pipe);

sys/dev/drm/drm_simple_kms_helper.c

99

struct drm_simple_display_pipe *pipe;

sys/dev/drm/drm_vblank.c

1019

static void drm_vblank_put(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

1021

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

1023

if (WARN_ON(pipe >= dev->num_crtcs))

sys/dev/drm/drm_vblank.c

1065

void drm_wait_one_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

1067

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

1071

if (WARN_ON(pipe >= dev->num_crtcs))

sys/dev/drm/drm_vblank.c

1074

ret = drm_vblank_get(dev, pipe);

sys/dev/drm/drm_vblank.c

1075

if (WARN(ret, "vblank not available on crtc %i, ret=%i\n", pipe, ret))

sys/dev/drm/drm_vblank.c

1078

last = drm_vblank_count(dev, pipe);

sys/dev/drm/drm_vblank.c

1081

last != drm_vblank_count(dev, pipe),

sys/dev/drm/drm_vblank.c

1084

WARN(ret == 0, "vblank wait timed out on crtc %i\n", pipe);

sys/dev/drm/drm_vblank.c

1086

drm_vblank_put(dev, pipe);

sys/dev/drm/drm_vblank.c

1118

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/drm/drm_vblank.c

1119

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

112

static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

1126

if (WARN_ON(pipe >= dev->num_crtcs))

sys/dev/drm/drm_vblank.c

1133

pipe, vblank->enabled, vblank->inmodeset);

sys/dev/drm/drm_vblank.c

1138

drm_vblank_disable_and_save(dev, pipe);

sys/dev/drm/drm_vblank.c

1153

seq = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/drm/drm_vblank.c

1156

if (e->pipe != pipe)

sys/dev/drm/drm_vblank.c

1162

drm_vblank_put(dev, pipe);

sys/dev/drm/drm_vblank.c

118

static u32 __get_vblank_counter(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

1189

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/drm/drm_vblank.c

1190

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

121

struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);

sys/dev/drm/drm_vblank.c

1220

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/drm/drm_vblank.c

1221

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

1224

if (WARN_ON(pipe >= dev->num_crtcs))

sys/dev/drm/drm_vblank.c

1229

pipe, vblank->enabled, vblank->inmodeset);

sys/dev/drm/drm_vblank.c

1237

drm_reset_vblank_timestamp(dev, pipe);

sys/dev/drm/drm_vblank.c

1244

WARN_ON(drm_vblank_enable(dev, pipe));

sys/dev/drm/drm_vblank.c

1262

void drm_vblank_restore(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

1271

if (WARN_ON(pipe >= dev->num_crtcs))

sys/dev/drm/drm_vblank.c

1277

vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

1283

cur_vblank = __get_vblank_counter(dev, pipe);

sys/dev/drm/drm_vblank.c

1284

drm_get_last_vbltimestamp(dev, pipe, &t_vblank, false);

sys/dev/drm/drm_vblank.c

1285

} while (cur_vblank != __get_vblank_counter(dev, pipe) && --count > 0);

sys/dev/drm/drm_vblank.c

1294

store_vblank(dev, pipe, diff, t_vblank, cur_vblank);

sys/dev/drm/drm_vblank.c

131

return dev->driver->get_vblank_counter(dev, pipe);

sys/dev/drm/drm_vblank.c

1315

unsigned int pipe)

sys/dev/drm/drm_vblank.c

1317

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

1323

if (WARN_ON(pipe >= dev->num_crtcs))

sys/dev/drm/drm_vblank.c

133

return drm_vblank_no_hw_counter(dev, pipe);

sys/dev/drm/drm_vblank.c

1335

if (drm_vblank_get(dev, pipe) == 0)

sys/dev/drm/drm_vblank.c

1341

unsigned int pipe)

sys/dev/drm/drm_vblank.c

1343

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

1350

if (WARN_ON(pipe >= dev->num_crtcs))

sys/dev/drm/drm_vblank.c

1355

drm_reset_vblank_timestamp(dev, pipe);

sys/dev/drm/drm_vblank.c

1359

drm_vblank_put(dev, pipe);

sys/dev/drm/drm_vblank.c

1369

unsigned int pipe;

sys/dev/drm/drm_vblank.c

1379

pipe = modeset->crtc;

sys/dev/drm/drm_vblank.c

1380

if (pipe >= dev->num_crtcs)

sys/dev/drm/drm_vblank.c

1385

drm_legacy_vblank_pre_modeset(dev, pipe);

sys/dev/drm/drm_vblank.c

1388

drm_legacy_vblank_post_modeset(dev, pipe);

sys/dev/drm/drm_vblank.c

1402

static int drm_queue_vblank_event(struct drm_device *dev, unsigned int pipe,

sys/dev/drm/drm_vblank.c

1407

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

1420

e->pipe = pipe;

sys/dev/drm/drm_vblank.c

1426

struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);

sys/dev/drm/drm_vblank.c

145

static void drm_reset_vblank_timestamp(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

1450

seq = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/drm/drm_vblank.c

1453

req_seq, seq, pipe);

sys/dev/drm/drm_vblank.c

1455

trace_drm_vblank_event_queued(file_priv, pipe, req_seq);

sys/dev/drm/drm_vblank.c

1459

drm_vblank_put(dev, pipe);

sys/dev/drm/drm_vblank.c

1476

drm_vblank_put(dev, pipe);

sys/dev/drm/drm_vblank.c

1507

static void drm_wait_vblank_reply(struct drm_device *dev, unsigned int pipe,

sys/dev/drm/drm_vblank.c

1518

reply->sequence = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/drm/drm_vblank.c

1533

unsigned int flags, pipe, high_pipe;

sys/dev/drm/drm_vblank.c

1560

pipe = 0;

sys/dev/drm/drm_vblank.c

1567

pipe++;

sys/dev/drm/drm_vblank.c

1570

pipe = pipe_index;

sys/dev/drm/drm_vblank.c

1573

if (pipe >= dev->num_crtcs)

sys/dev/drm/drm_vblank.c

1576

vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

1584

drm_wait_vblank_reply(dev, pipe, &vblwait->reply);

sys/dev/drm/drm_vblank.c

1588

ret = drm_vblank_get(dev, pipe);

sys/dev/drm/drm_vblank.c

159

cur_vblank = __get_vblank_counter(dev, pipe);

sys/dev/drm/drm_vblank.c

1590

DRM_DEBUG("crtc %d failed to acquire vblank counter, %d\n", pipe, ret);

sys/dev/drm/drm_vblank.c

1593

seq = drm_vblank_count(dev, pipe);

sys/dev/drm/drm_vblank.c

160

rc = drm_get_last_vbltimestamp(dev, pipe, &t_vblank, false);

sys/dev/drm/drm_vblank.c

161

} while (cur_vblank != __get_vblank_counter(dev, pipe) && --count > 0);

sys/dev/drm/drm_vblank.c

1620

return drm_queue_vblank_event(dev, pipe, req_seq, vblwait, file_priv);

sys/dev/drm/drm_vblank.c

1625

req_seq, pipe);

sys/dev/drm/drm_vblank.c

1627

vblank_passed(drm_vblank_count(dev, pipe),

sys/dev/drm/drm_vblank.c

1633

drm_wait_vblank_reply(dev, pipe, &vblwait->reply);

sys/dev/drm/drm_vblank.c

1636

pipe, vblwait->reply.sequence);

sys/dev/drm/drm_vblank.c

1638

DRM_DEBUG("crtc %d vblank wait interrupted by signal\n", pipe);

sys/dev/drm/drm_vblank.c

1642

drm_vblank_put(dev, pipe);

sys/dev/drm/drm_vblank.c

1646

static void drm_handle_vblank_events(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

1654

seq = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/drm/drm_vblank.c

1657

if (e->pipe != pipe)

sys/dev/drm/drm_vblank.c

1666

drm_vblank_put(dev, pipe);

sys/dev/drm/drm_vblank.c

1670

trace_drm_vblank_event(pipe, seq);

sys/dev/drm/drm_vblank.c

1683

bool drm_handle_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

1685

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

1692

if (WARN_ON(pipe >= dev->num_crtcs))

sys/dev/drm/drm_vblank.c

1710

drm_update_vblank_count(dev, pipe, true);

sys/dev/drm/drm_vblank.c

1725

drm_handle_vblank_events(dev, pipe);

sys/dev/drm/drm_vblank.c

175

store_vblank(dev, pipe, 1, t_vblank, cur_vblank);

sys/dev/drm/drm_vblank.c

1767

int pipe;

sys/dev/drm/drm_vblank.c

1783

pipe = drm_crtc_index(crtc);

sys/dev/drm/drm_vblank.c

1785

vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

1791

DRM_DEBUG("crtc %d failed to acquire vblank counter, %d\n", pipe, ret);

sys/dev/drm/drm_vblank.c

1801

get_seq->sequence = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/drm/drm_vblank.c

1821

int pipe;

sys/dev/drm/drm_vblank.c

1847

pipe = drm_crtc_index(crtc);

sys/dev/drm/drm_vblank.c

1849

vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

1857

DRM_DEBUG("crtc %d failed to acquire vblank counter, %d\n", pipe, ret);

sys/dev/drm/drm_vblank.c

1861

seq = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/drm/drm_vblank.c

1870

e->pipe = pipe;

sys/dev/drm/drm_vblank.c

192

static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe,

sys/dev/drm/drm_vblank.c

195

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

215

cur_vblank = __get_vblank_counter(dev, pipe);

sys/dev/drm/drm_vblank.c

216

rc = drm_get_last_vbltimestamp(dev, pipe, &t_vblank, in_vblank_irq);

sys/dev/drm/drm_vblank.c

217

} while (cur_vblank != __get_vblank_counter(dev, pipe) && --count > 0);

sys/dev/drm/drm_vblank.c

235

pipe, (long long) diff_ns, framedur_ns);

sys/dev/drm/drm_vblank.c

252

" due to pre-modeset.\n", pipe, diff);

sys/dev/drm/drm_vblank.c

258

pipe, vblank->count, diff, cur_vblank, vblank->last);

sys/dev/drm/drm_vblank.c

274

store_vblank(dev, pipe, diff, t_vblank, cur_vblank);

sys/dev/drm/drm_vblank.c

277

static u64 drm_vblank_count(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

279

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

281

if (WARN_ON(pipe >= dev->num_crtcs))

sys/dev/drm/drm_vblank.c

301

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/drm/drm_vblank.c

310

drm_update_vblank_count(dev, pipe, false);

sys/dev/drm/drm_vblank.c

311

vblank = drm_vblank_count(dev, pipe);

sys/dev/drm/drm_vblank.c

319

static void __disable_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

322

struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);

sys/dev/drm/drm_vblank.c

333

dev->driver->disable_vblank(dev, pipe);

sys/dev/drm/drm_vblank.c

342

void drm_vblank_disable_and_save(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

344

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

370

drm_update_vblank_count(dev, pipe, false);

sys/dev/drm/drm_vblank.c

371

__disable_vblank(dev, pipe);

sys/dev/drm/drm_vblank.c

382

unsigned int pipe = vblank->pipe;

sys/dev/drm/drm_vblank.c

387

DRM_DEBUG("disabling vblank on crtc %u\n", pipe);

sys/dev/drm/drm_vblank.c

388

drm_vblank_disable_and_save(dev, pipe);

sys/dev/drm/drm_vblank.c

395

unsigned int pipe;

sys/dev/drm/drm_vblank.c

401

for (pipe = 0; pipe < dev->num_crtcs; pipe++) {

sys/dev/drm/drm_vblank.c

402

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

445

vblank->pipe = i;

sys/dev/drm/drm_vblank.c

504

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/drm/drm_vblank.c

505

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

512

if (WARN_ON(pipe >= dev->num_crtcs))

sys/dev/drm/drm_vblank.c

580

unsigned int pipe,

sys/dev/drm/drm_vblank.c

590

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

597

crtc = drm_crtc_from_index(dev, pipe);

sys/dev/drm/drm_vblank.c

599

if (pipe >= dev->num_crtcs || !crtc) {

sys/dev/drm/drm_vblank.c

600

DRM_ERROR("Invalid crtc %u\n", pipe);

sys/dev/drm/drm_vblank.c

619

DRM_DEBUG("crtc %u: Noop due to uninitialized mode.\n", pipe);

sys/dev/drm/drm_vblank.c

637

vbl_status = dev->driver->get_scanout_position(dev, pipe,

sys/dev/drm/drm_vblank.c

646

pipe);

sys/dev/drm/drm_vblank.c

661

pipe, duration_ns/1000, *max_error/1000, i);

sys/dev/drm/drm_vblank.c

686

pipe, hpos, vpos,

sys/dev/drm/drm_vblank.c

717

drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,

sys/dev/drm/drm_vblank.c

727

ret = dev->driver->get_vblank_timestamp(dev, pipe, &max_error,

sys/dev/drm/drm_vblank.c

772

static u64 drm_vblank_count_and_time(struct drm_device *dev, unsigned int pipe,

sys/dev/drm/drm_vblank.c

775

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

779

if (WARN_ON(pipe >= dev->num_crtcs)) {

sys/dev/drm/drm_vblank.c

80

drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,

sys/dev/drm/drm_vblank.c

837

trace_drm_vblank_event_delivered(e->base.file_priv, e->pipe, seq);

sys/dev/drm/drm_vblank.c

883

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/drm/drm_vblank.c

887

e->pipe = pipe;

sys/dev/drm/drm_vblank.c

909

unsigned int pipe = drm_crtc_index(crtc);

sys/dev/drm/drm_vblank.c

913

seq = drm_vblank_count_and_time(dev, pipe, &now);

sys/dev/drm/drm_vblank.c

919

e->pipe = pipe;

sys/dev/drm/drm_vblank.c

92

static void store_vblank(struct drm_device *dev, unsigned int pipe,

sys/dev/drm/drm_vblank.c

924

static int __enable_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

927

struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);

sys/dev/drm/drm_vblank.c

936

return dev->driver->enable_vblank(dev, pipe);

sys/dev/drm/drm_vblank.c

939

static int drm_vblank_enable(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

941

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

956

ret = __enable_vblank(dev, pipe);

sys/dev/drm/drm_vblank.c

957

DRM_DEBUG("enabling vblank on crtc %u, ret: %d\n", pipe, ret);

sys/dev/drm/drm_vblank.c

96

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

961

drm_update_vblank_count(dev, pipe, 0);

sys/dev/drm/drm_vblank.c

976

static int drm_vblank_get(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/drm_vblank.c

978

struct drm_vblank_crtc *vblank = &dev->vblank[pipe];

sys/dev/drm/drm_vblank.c

985

if (WARN_ON(pipe >= dev->num_crtcs))

sys/dev/drm/drm_vblank.c

991

ret = drm_vblank_enable(dev, pipe);

sys/dev/drm/i915/i915_drv.h

1196

struct g4x_pipe_wm pipe[3];

sys/dev/drm/i915/i915_drv.h

1204

struct g4x_pipe_wm pipe[2];

sys/dev/drm/i915/i915_drv.h

2248

#define INTEL_FRONTBUFFER(pipe, plane_id) ({ \

sys/dev/drm/i915/i915_drv.h

2251

BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \

sys/dev/drm/i915/i915_drv.h

2253

#define INTEL_FRONTBUFFER_OVERLAY(pipe) \

sys/dev/drm/i915/i915_drv.h

2254

BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))

sys/dev/drm/i915/i915_drv.h

2255

#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \

sys/dev/drm/i915/i915_drv.h

2256

GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \

sys/dev/drm/i915/i915_drv.h

2257

INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))

sys/dev/drm/i915/i915_drv.h

2855

enum i915_pipe pipe);

sys/dev/drm/i915/i915_drv.h

2857

i915_enable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,

sys/dev/drm/i915/i915_drv.h

2861

i915_disable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe,

sys/dev/drm/i915/i915_drv.h

2883

enum i915_pipe pipe,

sys/dev/drm/i915/i915_drv.h

2887

enum i915_pipe pipe, uint32_t bits)

sys/dev/drm/i915/i915_drv.h

2889

bdw_update_pipe_irq(dev_priv, pipe, bits, bits);

sys/dev/drm/i915/i915_drv.h

2892

enum i915_pipe pipe, uint32_t bits)

sys/dev/drm/i915/i915_drv.h

2894

bdw_update_pipe_irq(dev_priv, pipe, bits, 0);

sys/dev/drm/i915/i915_drv.h

3438

enum i915_pipe pipe, enum port port,

sys/dev/drm/i915/i915_drv.h

3544

u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg);

sys/dev/drm/i915/i915_drv.h

3545

void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val);

sys/dev/drm/i915/i915_drv.h

569

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

1004

"pipe %c\n", pipe_name(pipe));

sys/dev/drm/i915/i915_irq.c

1043

position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;

sys/dev/drm/i915/i915_irq.c

1740

enum i915_pipe pipe,

sys/dev/drm/i915/i915_irq.c

1745

struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];

sys/dev/drm/i915/i915_irq.c

1746

struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

1778

enum i915_pipe pipe,

sys/dev/drm/i915/i915_irq.c

1786

enum i915_pipe pipe)

sys/dev/drm/i915/i915_irq.c

1788

display_pipe_crc_irq_handler(dev_priv, pipe,

sys/dev/drm/i915/i915_irq.c

1789

I915_READ(PIPE_CRC_RES_1_IVB(pipe)),

sys/dev/drm/i915/i915_irq.c

1794

enum i915_pipe pipe)

sys/dev/drm/i915/i915_irq.c

1796

display_pipe_crc_irq_handler(dev_priv, pipe,

sys/dev/drm/i915/i915_irq.c

1797

I915_READ(PIPE_CRC_RES_1_IVB(pipe)),

sys/dev/drm/i915/i915_irq.c

1798

I915_READ(PIPE_CRC_RES_2_IVB(pipe)),

sys/dev/drm/i915/i915_irq.c

1799

I915_READ(PIPE_CRC_RES_3_IVB(pipe)),

sys/dev/drm/i915/i915_irq.c

1800

I915_READ(PIPE_CRC_RES_4_IVB(pipe)),

sys/dev/drm/i915/i915_irq.c

1801

I915_READ(PIPE_CRC_RES_5_IVB(pipe)));

sys/dev/drm/i915/i915_irq.c

1805

enum i915_pipe pipe)

sys/dev/drm/i915/i915_irq.c

1810

res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));

sys/dev/drm/i915/i915_irq.c

1815

res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));

sys/dev/drm/i915/i915_irq.c

1819

display_pipe_crc_irq_handler(dev_priv, pipe,

sys/dev/drm/i915/i915_irq.c

1820

I915_READ(PIPE_CRC_RES_RED(pipe)),

sys/dev/drm/i915/i915_irq.c

1821

I915_READ(PIPE_CRC_RES_GREEN(pipe)),

sys/dev/drm/i915/i915_irq.c

1822

I915_READ(PIPE_CRC_RES_BLUE(pipe)),

sys/dev/drm/i915/i915_irq.c

1863

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

1865

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/i915_irq.c

1866

I915_WRITE(PIPESTAT(pipe),

sys/dev/drm/i915/i915_irq.c

1870

dev_priv->pipestat_irq_mask[pipe] = 0;

sys/dev/drm/i915/i915_irq.c

1877

int pipe;

sys/dev/drm/i915/i915_irq.c

1886

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/i915_irq.c

1901

switch (pipe) {

sys/dev/drm/i915/i915_irq.c

1913

status_mask |= dev_priv->pipestat_irq_mask[pipe];

sys/dev/drm/i915/i915_irq.c

1918

reg = PIPESTAT(pipe);

sys/dev/drm/i915/i915_irq.c

1919

pipe_stats[pipe] = I915_READ(reg) & status_mask;

sys/dev/drm/i915/i915_irq.c

1920

enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

1931

if (pipe_stats[pipe]) {

sys/dev/drm/i915/i915_irq.c

1932

I915_WRITE(reg, pipe_stats[pipe]);

sys/dev/drm/i915/i915_irq.c

1942

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

1944

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/i915_irq.c

1945

if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)

sys/dev/drm/i915/i915_irq.c

1946

drm_handle_vblank(&dev_priv->drm, pipe);

sys/dev/drm/i915/i915_irq.c

1948

if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)

sys/dev/drm/i915/i915_irq.c

1949

i9xx_pipe_crc_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

1951

if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

sys/dev/drm/i915/i915_irq.c

1952

intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

1960

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

1962

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/i915_irq.c

1963

if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)

sys/dev/drm/i915/i915_irq.c

1964

drm_handle_vblank(&dev_priv->drm, pipe);

sys/dev/drm/i915/i915_irq.c

1966

if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)

sys/dev/drm/i915/i915_irq.c

1969

if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)

sys/dev/drm/i915/i915_irq.c

1970

i9xx_pipe_crc_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

1972

if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

sys/dev/drm/i915/i915_irq.c

1973

intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

1984

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

1986

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/i915_irq.c

1987

if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)

sys/dev/drm/i915/i915_irq.c

1988

drm_handle_vblank(&dev_priv->drm, pipe);

sys/dev/drm/i915/i915_irq.c

1990

if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)

sys/dev/drm/i915/i915_irq.c

1993

if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)

sys/dev/drm/i915/i915_irq.c

1994

i9xx_pipe_crc_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

1996

if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

sys/dev/drm/i915/i915_irq.c

1997

intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

2010

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

2012

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/i915_irq.c

2013

if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)

sys/dev/drm/i915/i915_irq.c

2014

drm_handle_vblank(&dev_priv->drm, pipe);

sys/dev/drm/i915/i915_irq.c

2016

if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)

sys/dev/drm/i915/i915_irq.c

2017

i9xx_pipe_crc_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

2019

if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)

sys/dev/drm/i915/i915_irq.c

2020

intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

2299

int pipe;

sys/dev/drm/i915/i915_irq.c

2327

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/i915_irq.c

2329

pipe_name(pipe),

sys/dev/drm/i915/i915_irq.c

2330

I915_READ(FDI_RX_IIR(pipe)));

sys/dev/drm/i915/i915_irq.c

2348

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

2353

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/i915_irq.c

2354

if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))

sys/dev/drm/i915/i915_irq.c

2355

intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

2357

if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {

sys/dev/drm/i915/i915_irq.c

2359

ivb_pipe_crc_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

2361

hsw_pipe_crc_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

2371

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

2376

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/i915_irq.c

2377

if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))

sys/dev/drm/i915/i915_irq.c

2378

intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

2385

int pipe;

sys/dev/drm/i915/i915_irq.c

2410

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/i915_irq.c

2412

pipe_name(pipe),

sys/dev/drm/i915/i915_irq.c

2413

I915_READ(FDI_RX_IIR(pipe)));

sys/dev/drm/i915/i915_irq.c

2511

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

2526

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/i915_irq.c

2527

if (de_iir & DE_PIPE_VBLANK(pipe))

sys/dev/drm/i915/i915_irq.c

2528

drm_handle_vblank(&dev_priv->drm, pipe);

sys/dev/drm/i915/i915_irq.c

2530

if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))

sys/dev/drm/i915/i915_irq.c

2531

intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

2533

if (de_iir & DE_PIPE_CRC_DONE(pipe))

sys/dev/drm/i915/i915_irq.c

2534

i9xx_pipe_crc_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

2557

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

2579

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/i915_irq.c

2580

if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))

sys/dev/drm/i915/i915_irq.c

2581

drm_handle_vblank(&dev_priv->drm, pipe);

sys/dev/drm/i915/i915_irq.c

2726

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

2822

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/i915_irq.c

2825

if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))

sys/dev/drm/i915/i915_irq.c

2828

iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));

sys/dev/drm/i915/i915_irq.c

2835

I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);

sys/dev/drm/i915/i915_irq.c

2838

drm_handle_vblank(&dev_priv->drm, pipe);

sys/dev/drm/i915/i915_irq.c

2841

hsw_pipe_crc_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

2844

intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

2854

pipe_name(pipe),

sys/dev/drm/i915/i915_irq.c

3363

static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/i915/i915_irq.c

3369

i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);

sys/dev/drm/i915/i915_irq.c

3375

static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/i915/i915_irq.c

3381

i915_enable_pipestat(dev_priv, pipe,

sys/dev/drm/i915/i915_irq.c

3388

static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/i915/i915_irq.c

3393

DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);

sys/dev/drm/i915/i915_irq.c

3403

drm_vblank_restore(dev, pipe);

sys/dev/drm/i915/i915_irq.c

3408

static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/i915/i915_irq.c

3414

bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);

sys/dev/drm/i915/i915_irq.c

3421

drm_vblank_restore(dev, pipe);

sys/dev/drm/i915/i915_irq.c

3429

static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/i915/i915_irq.c

3435

i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);

sys/dev/drm/i915/i915_irq.c

3439

static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/i915/i915_irq.c

3445

i915_disable_pipestat(dev_priv, pipe,

sys/dev/drm/i915/i915_irq.c

3450

static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/i915/i915_irq.c

3455

DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);

sys/dev/drm/i915/i915_irq.c

3462

static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/i915/i915_irq.c

3468

bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);

sys/dev/drm/i915/i915_irq.c

3530

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

3535

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/i915_irq.c

3536

i915_enable_pipestat(dev_priv, pipe, pipestat_mask);

sys/dev/drm/i915/i915_irq.c

3604

int pipe;

sys/dev/drm/i915/i915_irq.c

3614

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/i915_irq.c

3616

POWER_DOMAIN_PIPE(pipe)))

sys/dev/drm/i915/i915_irq.c

3617

GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);

sys/dev/drm/i915/i915_irq.c

3647

int pipe;

sys/dev/drm/i915/i915_irq.c

3656

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/i915_irq.c

3658

POWER_DOMAIN_PIPE(pipe)))

sys/dev/drm/i915/i915_irq.c

3659

GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);

sys/dev/drm/i915/i915_irq.c

3675

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

3684

for_each_pipe_masked(dev_priv, pipe, pipe_mask)

sys/dev/drm/i915/i915_irq.c

3685

GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,

sys/dev/drm/i915/i915_irq.c

3686

dev_priv->de_irq_mask[pipe],

sys/dev/drm/i915/i915_irq.c

3687

~dev_priv->de_irq_mask[pipe] | extra_ier);

sys/dev/drm/i915/i915_irq.c

3695

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

3704

for_each_pipe_masked(dev_priv, pipe, pipe_mask)

sys/dev/drm/i915/i915_irq.c

3705

GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);

sys/dev/drm/i915/i915_irq.c

4179

enum i915_pipe pipe;

sys/dev/drm/i915/i915_irq.c

4212

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/i915_irq.c

4213

dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;

sys/dev/drm/i915/i915_irq.c

4216

POWER_DOMAIN_PIPE(pipe)))

sys/dev/drm/i915/i915_irq.c

4217

GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,

sys/dev/drm/i915/i915_irq.c

4218

dev_priv->de_irq_mask[pipe],

sys/dev/drm/i915/i915_irq.c

614

enum i915_pipe pipe,

sys/dev/drm/i915/i915_irq.c

627

new_val = dev_priv->de_irq_mask[pipe];

sys/dev/drm/i915/i915_irq.c

631

if (new_val != dev_priv->de_irq_mask[pipe]) {

sys/dev/drm/i915/i915_irq.c

632

dev_priv->de_irq_mask[pipe] = new_val;

sys/dev/drm/i915/i915_irq.c

633

I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);

sys/dev/drm/i915/i915_irq.c

634

POSTING_READ(GEN8_DE_PIPE_IMR(pipe));

sys/dev/drm/i915/i915_irq.c

664

enum i915_pipe pipe)

sys/dev/drm/i915/i915_irq.c

666

u32 status_mask = dev_priv->pipestat_irq_mask[pipe];

sys/dev/drm/i915/i915_irq.c

699

pipe_name(pipe), enable_mask, status_mask);

sys/dev/drm/i915/i915_irq.c

705

enum i915_pipe pipe, u32 status_mask)

sys/dev/drm/i915/i915_irq.c

707

i915_reg_t reg = PIPESTAT(pipe);

sys/dev/drm/i915/i915_irq.c

712

pipe_name(pipe), status_mask);

sys/dev/drm/i915/i915_irq.c

717

if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)

sys/dev/drm/i915/i915_irq.c

720

dev_priv->pipestat_irq_mask[pipe] |= status_mask;

sys/dev/drm/i915/i915_irq.c

721

enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

728

enum i915_pipe pipe, u32 status_mask)

sys/dev/drm/i915/i915_irq.c

730

i915_reg_t reg = PIPESTAT(pipe);

sys/dev/drm/i915/i915_irq.c

735

pipe_name(pipe), status_mask);

sys/dev/drm/i915/i915_irq.c

740

if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)

sys/dev/drm/i915/i915_irq.c

743

dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;

sys/dev/drm/i915/i915_irq.c

744

enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);

sys/dev/drm/i915/i915_irq.c

822

static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/i915/i915_irq.c

827

const struct drm_display_mode *mode = &dev->vblank[pipe].hwmode;

sys/dev/drm/i915/i915_irq.c

842

high_frame = PIPEFRAME(pipe);

sys/dev/drm/i915/i915_irq.c

843

low_frame = PIPEFRAMEPIXEL(pipe);

sys/dev/drm/i915/i915_irq.c

872

static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/i915/i915_irq.c

876

return I915_READ(PIPE_FRMCOUNT_G4X(pipe));

sys/dev/drm/i915/i915_irq.c

911

scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));

sys/dev/drm/i915/i915_irq.c

919

scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));

sys/dev/drm/i915/i915_irq.c

937

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/i915_irq.c

954

position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;

sys/dev/drm/i915/i915_irq.c

956

position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;

sys/dev/drm/i915/i915_irq.c

975

temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;

sys/dev/drm/i915/i915_irq.c

990

static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,

sys/dev/drm/i915/i915_irq.c

997

pipe);

sys/dev/drm/i915/i915_reg.h

1018

#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))

sys/dev/drm/i915/i915_reg.h

1019

#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))

sys/dev/drm/i915/i915_reg.h

1020

#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))

sys/dev/drm/i915/i915_reg.h

1021

#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))

sys/dev/drm/i915/i915_reg.h

1022

#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))

sys/dev/drm/i915/i915_reg.h

1023

#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))

sys/dev/drm/i915/i915_reg.h

1024

#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))

sys/dev/drm/i915/i915_reg.h

1025

#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))

sys/dev/drm/i915/i915_reg.h

1026

#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))

sys/dev/drm/i915/i915_reg.h

1027

#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))

sys/dev/drm/i915/i915_reg.h

1028

#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))

sys/dev/drm/i915/i915_reg.h

1029

#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))

sys/dev/drm/i915/i915_reg.h

10353

#define BXT_PIPE_SELECT(pipe) ((pipe) << 7)

sys/dev/drm/i915/i915_reg.h

10451

#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10454

#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10472

#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10475

#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10486

#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10489

#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10501

#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10504

#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10516

#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10519

#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10531

#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10534

#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10546

#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10549

#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10563

#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10566

#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10578

#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10581

#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10593

#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10596

#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10608

#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10611

#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10625

#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10628

#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10638

#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10641

#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10651

#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10654

#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10664

#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10667

#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10677

#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10680

#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10690

#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10693

#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10712

#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10715

#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10718

#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10721

#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10737

#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10740

#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10743

#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

10746

#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

1176

#define DPIO_PHY(pipe) ((pipe) >> 1)

sys/dev/drm/i915/i915_reg.h

160

#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b)

sys/dev/drm/i915/i915_reg.h

161

#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))

sys/dev/drm/i915/i915_reg.h

168

#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))

sys/dev/drm/i915/i915_reg.h

169

#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))

sys/dev/drm/i915/i915_reg.h

2498

#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))

sys/dev/drm/i915/i915_reg.h

2500

#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))

sys/dev/drm/i915/i915_reg.h

2682

#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \

sys/dev/drm/i915/i915_reg.h

3175

#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)

sys/dev/drm/i915/i915_reg.h

3274

#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)

sys/dev/drm/i915/i915_reg.h

3319

#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)

sys/dev/drm/i915/i915_reg.h

3320

#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)

sys/dev/drm/i915/i915_reg.h

3485

#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \

sys/dev/drm/i915/i915_reg.h

3953

#define CLKGATE_DIS_PSL(pipe) \

sys/dev/drm/i915/i915_reg.h

3954

_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)

sys/dev/drm/i915/i915_reg.h

4031

#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)

sys/dev/drm/i915/i915_reg.h

4032

#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)

sys/dev/drm/i915/i915_reg.h

4033

#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)

sys/dev/drm/i915/i915_reg.h

4034

#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)

sys/dev/drm/i915/i915_reg.h

4035

#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)

sys/dev/drm/i915/i915_reg.h

4036

#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)

sys/dev/drm/i915/i915_reg.h

4038

#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)

sys/dev/drm/i915/i915_reg.h

4039

#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)

sys/dev/drm/i915/i915_reg.h

4040

#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)

sys/dev/drm/i915/i915_reg.h

4041

#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)

sys/dev/drm/i915/i915_reg.h

4042

#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)

sys/dev/drm/i915/i915_reg.h

4074

#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \

sys/dev/drm/i915/i915_reg.h

4103

#define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)

sys/dev/drm/i915/i915_reg.h

4110

#define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)

sys/dev/drm/i915/i915_reg.h

4123

#define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)

sys/dev/drm/i915/i915_reg.h

4259

#define ADPA_PIPE_SEL(pipe) ((pipe) << 30)

sys/dev/drm/i915/i915_reg.h

4262

#define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)

sys/dev/drm/i915/i915_reg.h

4423

#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)

sys/dev/drm/i915/i915_reg.h

4465

#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)

sys/dev/drm/i915/i915_reg.h

4470

#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)

sys/dev/drm/i915/i915_reg.h

4483

#define DVO_PIPE_SEL(pipe) ((pipe) << 30)

sys/dev/drm/i915/i915_reg.h

4522

#define LVDS_PIPE_SEL(pipe) ((pipe) << 30)

sys/dev/drm/i915/i915_reg.h

4525

#define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)

sys/dev/drm/i915/i915_reg.h

4720

#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \

sys/dev/drm/i915/i915_reg.h

4725

#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \

sys/dev/drm/i915/i915_reg.h

4730

#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \

sys/dev/drm/i915/i915_reg.h

4746

#define BLM_PIPE(pipe) ((pipe) << 29)

sys/dev/drm/i915/i915_reg.h

4834

# define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)

sys/dev/drm/i915/i915_reg.h

5318

#define DP_PIPE_SEL(pipe) ((pipe) << 30)

sys/dev/drm/i915/i915_reg.h

5321

#define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)

sys/dev/drm/i915/i915_reg.h

5324

#define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)

sys/dev/drm/i915/i915_reg.h

5524

#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)

sys/dev/drm/i915/i915_reg.h

5525

#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)

sys/dev/drm/i915/i915_reg.h

5526

#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)

sys/dev/drm/i915/i915_reg.h

5527

#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)

sys/dev/drm/i915/i915_reg.h

5643

#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \

sys/dev/drm/i915/i915_reg.h

5647

#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)

sys/dev/drm/i915/i915_reg.h

5648

#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)

sys/dev/drm/i915/i915_reg.h

5649

#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)

sys/dev/drm/i915/i915_reg.h

5650

#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)

sys/dev/drm/i915/i915_reg.h

5651

#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)

sys/dev/drm/i915/i915_reg.h

5666

#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)

sys/dev/drm/i915/i915_reg.h

5885

#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))

sys/dev/drm/i915/i915_reg.h

5898

#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */

sys/dev/drm/i915/i915_reg.h

5951

#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)

sys/dev/drm/i915/i915_reg.h

5952

#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))

sys/dev/drm/i915/i915_reg.h

5953

#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)

sys/dev/drm/i915/i915_reg.h

5955

#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)

sys/dev/drm/i915/i915_reg.h

5956

#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)

sys/dev/drm/i915/i915_reg.h

5957

#define _PLANE_WM_BASE(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

5958

_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))

sys/dev/drm/i915/i915_reg.h

5959

#define PLANE_WM(pipe, plane, level) \

sys/dev/drm/i915/i915_reg.h

5960

_MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))

sys/dev/drm/i915/i915_reg.h

5961

#define _PLANE_WM_TRANS_1(pipe) \

sys/dev/drm/i915/i915_reg.h

5962

_PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)

sys/dev/drm/i915/i915_reg.h

5963

#define _PLANE_WM_TRANS_2(pipe) \

sys/dev/drm/i915/i915_reg.h

5964

_PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)

sys/dev/drm/i915/i915_reg.h

5965

#define PLANE_WM_TRANS(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

5966

_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))

sys/dev/drm/i915/i915_reg.h

6043

#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)

sys/dev/drm/i915/i915_reg.h

6044

#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)

sys/dev/drm/i915/i915_reg.h

6071

#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)

sys/dev/drm/i915/i915_reg.h

6094

#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \

sys/dev/drm/i915/i915_reg.h

6098

#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)

sys/dev/drm/i915/i915_reg.h

6099

#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)

sys/dev/drm/i915/i915_reg.h

6100

#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)

sys/dev/drm/i915/i915_reg.h

6101

#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)

sys/dev/drm/i915/i915_reg.h

6102

#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)

sys/dev/drm/i915/i915_reg.h

6135

#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)

sys/dev/drm/i915/i915_reg.h

6179

#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)

sys/dev/drm/i915/i915_reg.h

6180

#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)

sys/dev/drm/i915/i915_reg.h

6288

#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)

sys/dev/drm/i915/i915_reg.h

6289

#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)

sys/dev/drm/i915/i915_reg.h

6290

#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)

sys/dev/drm/i915/i915_reg.h

6291

#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)

sys/dev/drm/i915/i915_reg.h

6292

#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)

sys/dev/drm/i915/i915_reg.h

6293

#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)

sys/dev/drm/i915/i915_reg.h

6294

#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)

sys/dev/drm/i915/i915_reg.h

6295

#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)

sys/dev/drm/i915/i915_reg.h

6296

#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)

sys/dev/drm/i915/i915_reg.h

6297

#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)

sys/dev/drm/i915/i915_reg.h

6298

#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)

sys/dev/drm/i915/i915_reg.h

6299

#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)

sys/dev/drm/i915/i915_reg.h

6363

#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)

sys/dev/drm/i915/i915_reg.h

6364

#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)

sys/dev/drm/i915/i915_reg.h

6365

#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)

sys/dev/drm/i915/i915_reg.h

6366

#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)

sys/dev/drm/i915/i915_reg.h

6367

#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)

sys/dev/drm/i915/i915_reg.h

6368

#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)

sys/dev/drm/i915/i915_reg.h

6369

#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)

sys/dev/drm/i915/i915_reg.h

6370

#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)

sys/dev/drm/i915/i915_reg.h

6371

#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)

sys/dev/drm/i915/i915_reg.h

6372

#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)

sys/dev/drm/i915/i915_reg.h

6373

#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)

sys/dev/drm/i915/i915_reg.h

6374

#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)

sys/dev/drm/i915/i915_reg.h

6375

#define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)

sys/dev/drm/i915/i915_reg.h

6376

#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)

sys/dev/drm/i915/i915_reg.h

6435

#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \

sys/dev/drm/i915/i915_reg.h

6436

_MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))

sys/dev/drm/i915/i915_reg.h

6438

#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)

sys/dev/drm/i915/i915_reg.h

6439

#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)

sys/dev/drm/i915/i915_reg.h

6440

#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)

sys/dev/drm/i915/i915_reg.h

6441

#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)

sys/dev/drm/i915/i915_reg.h

6442

#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)

sys/dev/drm/i915/i915_reg.h

6443

#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)

sys/dev/drm/i915/i915_reg.h

6444

#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)

sys/dev/drm/i915/i915_reg.h

6445

#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)

sys/dev/drm/i915/i915_reg.h

6446

#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)

sys/dev/drm/i915/i915_reg.h

6447

#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)

sys/dev/drm/i915/i915_reg.h

6448

#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)

sys/dev/drm/i915/i915_reg.h

6449

#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)

sys/dev/drm/i915/i915_reg.h

6450

#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)

sys/dev/drm/i915/i915_reg.h

6451

#define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)

sys/dev/drm/i915/i915_reg.h

6592

#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)

sys/dev/drm/i915/i915_reg.h

6593

#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)

sys/dev/drm/i915/i915_reg.h

6594

#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)

sys/dev/drm/i915/i915_reg.h

6595

#define PLANE_CTL(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6596

_MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))

sys/dev/drm/i915/i915_reg.h

6601

#define _PLANE_STRIDE_1(pipe) \

sys/dev/drm/i915/i915_reg.h

6602

_PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)

sys/dev/drm/i915/i915_reg.h

6603

#define _PLANE_STRIDE_2(pipe) \

sys/dev/drm/i915/i915_reg.h

6604

_PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)

sys/dev/drm/i915/i915_reg.h

6605

#define _PLANE_STRIDE_3(pipe) \

sys/dev/drm/i915/i915_reg.h

6606

_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)

sys/dev/drm/i915/i915_reg.h

6607

#define PLANE_STRIDE(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6608

_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))

sys/dev/drm/i915/i915_reg.h

6613

#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)

sys/dev/drm/i915/i915_reg.h

6614

#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)

sys/dev/drm/i915/i915_reg.h

6615

#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)

sys/dev/drm/i915/i915_reg.h

6616

#define PLANE_POS(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6617

_MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))

sys/dev/drm/i915/i915_reg.h

6622

#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)

sys/dev/drm/i915/i915_reg.h

6623

#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)

sys/dev/drm/i915/i915_reg.h

6624

#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)

sys/dev/drm/i915/i915_reg.h

6625

#define PLANE_SIZE(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6626

_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))

sys/dev/drm/i915/i915_reg.h

6631

#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)

sys/dev/drm/i915/i915_reg.h

6632

#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)

sys/dev/drm/i915/i915_reg.h

6633

#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)

sys/dev/drm/i915/i915_reg.h

6634

#define PLANE_SURF(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6635

_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))

sys/dev/drm/i915/i915_reg.h

6639

#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)

sys/dev/drm/i915/i915_reg.h

6640

#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)

sys/dev/drm/i915/i915_reg.h

6641

#define PLANE_OFFSET(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6642

_MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))

sys/dev/drm/i915/i915_reg.h

6646

#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)

sys/dev/drm/i915/i915_reg.h

6647

#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)

sys/dev/drm/i915/i915_reg.h

6648

#define PLANE_KEYVAL(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6649

_MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))

sys/dev/drm/i915/i915_reg.h

6653

#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)

sys/dev/drm/i915/i915_reg.h

6654

#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)

sys/dev/drm/i915/i915_reg.h

6655

#define PLANE_KEYMSK(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6656

_MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))

sys/dev/drm/i915/i915_reg.h

6660

#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)

sys/dev/drm/i915/i915_reg.h

6661

#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)

sys/dev/drm/i915/i915_reg.h

6662

#define PLANE_KEYMAX(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6663

_MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))

sys/dev/drm/i915/i915_reg.h

6670

#define _PLANE_BUF_CFG_1(pipe) \

sys/dev/drm/i915/i915_reg.h

6671

_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)

sys/dev/drm/i915/i915_reg.h

6672

#define _PLANE_BUF_CFG_2(pipe) \

sys/dev/drm/i915/i915_reg.h

6673

_PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)

sys/dev/drm/i915/i915_reg.h

6674

#define PLANE_BUF_CFG(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6675

_MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))

sys/dev/drm/i915/i915_reg.h

6679

#define _PLANE_NV12_BUF_CFG_1(pipe) \

sys/dev/drm/i915/i915_reg.h

6680

_PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)

sys/dev/drm/i915/i915_reg.h

6681

#define _PLANE_NV12_BUF_CFG_2(pipe) \

sys/dev/drm/i915/i915_reg.h

6682

_PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)

sys/dev/drm/i915/i915_reg.h

6683

#define PLANE_NV12_BUF_CFG(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6684

_MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))

sys/dev/drm/i915/i915_reg.h

6688

#define _PLANE_AUX_DIST_1(pipe) \

sys/dev/drm/i915/i915_reg.h

6689

_PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)

sys/dev/drm/i915/i915_reg.h

6690

#define _PLANE_AUX_DIST_2(pipe) \

sys/dev/drm/i915/i915_reg.h

6691

_PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)

sys/dev/drm/i915/i915_reg.h

6692

#define PLANE_AUX_DIST(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6693

_MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))

sys/dev/drm/i915/i915_reg.h

6697

#define _PLANE_AUX_OFFSET_1(pipe) \

sys/dev/drm/i915/i915_reg.h

6698

_PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)

sys/dev/drm/i915/i915_reg.h

6699

#define _PLANE_AUX_OFFSET_2(pipe) \

sys/dev/drm/i915/i915_reg.h

6700

_PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)

sys/dev/drm/i915/i915_reg.h

6701

#define PLANE_AUX_OFFSET(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6702

_MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))

sys/dev/drm/i915/i915_reg.h

6707

#define _PLANE_COLOR_CTL_1(pipe) \

sys/dev/drm/i915/i915_reg.h

6708

_PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)

sys/dev/drm/i915/i915_reg.h

6709

#define _PLANE_COLOR_CTL_2(pipe) \

sys/dev/drm/i915/i915_reg.h

6710

_PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)

sys/dev/drm/i915/i915_reg.h

6711

#define PLANE_COLOR_CTL(pipe, plane) \

sys/dev/drm/i915/i915_reg.h

6712

_MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))

sys/dev/drm/i915/i915_reg.h

6717

#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)

sys/dev/drm/i915/i915_reg.h

6815

#define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29)

sys/dev/drm/i915/i915_reg.h

6830

#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)

sys/dev/drm/i915/i915_reg.h

6831

#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)

sys/dev/drm/i915/i915_reg.h

6832

#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)

sys/dev/drm/i915/i915_reg.h

6833

#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)

sys/dev/drm/i915/i915_reg.h

6834

#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)

sys/dev/drm/i915/i915_reg.h

6844

#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)

sys/dev/drm/i915/i915_reg.h

6845

#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)

sys/dev/drm/i915/i915_reg.h

6846

#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)

sys/dev/drm/i915/i915_reg.h

6941

#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/drm/i915/i915_reg.h

6944

#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/drm/i915/i915_reg.h

6947

#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/drm/i915/i915_reg.h

6950

#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/drm/i915/i915_reg.h

6953

#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/drm/i915/i915_reg.h

6956

#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/drm/i915/i915_reg.h

6959

#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/drm/i915/i915_reg.h

6962

#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/drm/i915/i915_reg.h

6965

#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \

sys/dev/drm/i915/i915_reg.h

6972

#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)

sys/dev/drm/i915/i915_reg.h

6976

#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)

sys/dev/drm/i915/i915_reg.h

7021

#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))

sys/dev/drm/i915/i915_reg.h

7027

#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))

sys/dev/drm/i915/i915_reg.h

7029

#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))

sys/dev/drm/i915/i915_reg.h

7048

#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))

sys/dev/drm/i915/i915_reg.h

7072

#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))

sys/dev/drm/i915/i915_reg.h

7103

#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))

sys/dev/drm/i915/i915_reg.h

7104

#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))

sys/dev/drm/i915/i915_reg.h

7105

#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))

sys/dev/drm/i915/i915_reg.h

7106

#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))

sys/dev/drm/i915/i915_reg.h

7322

#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)

sys/dev/drm/i915/i915_reg.h

7484

#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\

sys/dev/drm/i915/i915_reg.h

7604

#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))

sys/dev/drm/i915/i915_reg.h

7691

#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7694

#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7697

#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7700

#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7719

#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7722

#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7725

#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7728

#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7744

#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7747

#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7750

#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7753

#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7769

#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7772

#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7775

#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7778

#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \

sys/dev/drm/i915/i915_reg.h

7841

#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))

sys/dev/drm/i915/i915_reg.h

7842

#define TRANS_DPLLA_SEL(pipe) 0

sys/dev/drm/i915/i915_reg.h

7843

#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))

sys/dev/drm/i915/i915_reg.h

7888

#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)

sys/dev/drm/i915/i915_reg.h

7889

#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)

sys/dev/drm/i915/i915_reg.h

7890

#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)

sys/dev/drm/i915/i915_reg.h

7905

#define VLV_TVIDEO_DIP_CTL(pipe) \

sys/dev/drm/i915/i915_reg.h

7906

_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \

sys/dev/drm/i915/i915_reg.h

7908

#define VLV_TVIDEO_DIP_DATA(pipe) \

sys/dev/drm/i915/i915_reg.h

7909

_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \

sys/dev/drm/i915/i915_reg.h

7911

#define VLV_TVIDEO_DIP_GCP(pipe) \

sys/dev/drm/i915/i915_reg.h

7912

_MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \

sys/dev/drm/i915/i915_reg.h

7977

#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)

sys/dev/drm/i915/i915_reg.h

7978

#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)

sys/dev/drm/i915/i915_reg.h

7979

#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)

sys/dev/drm/i915/i915_reg.h

7980

#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)

sys/dev/drm/i915/i915_reg.h

7981

#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)

sys/dev/drm/i915/i915_reg.h

7982

#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)

sys/dev/drm/i915/i915_reg.h

7983

#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)

sys/dev/drm/i915/i915_reg.h

7994

#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)

sys/dev/drm/i915/i915_reg.h

7995

#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)

sys/dev/drm/i915/i915_reg.h

7996

#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)

sys/dev/drm/i915/i915_reg.h

7997

#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)

sys/dev/drm/i915/i915_reg.h

7998

#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)

sys/dev/drm/i915/i915_reg.h

7999

#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)

sys/dev/drm/i915/i915_reg.h

8000

#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)

sys/dev/drm/i915/i915_reg.h

8001

#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)

sys/dev/drm/i915/i915_reg.h

8005

#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)

sys/dev/drm/i915/i915_reg.h

8027

#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)

sys/dev/drm/i915/i915_reg.h

8032

#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)

sys/dev/drm/i915/i915_reg.h

8042

#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))

sys/dev/drm/i915/i915_reg.h

8043

#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))

sys/dev/drm/i915/i915_reg.h

8058

#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)

sys/dev/drm/i915/i915_reg.h

8071

#define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)

sys/dev/drm/i915/i915_reg.h

8121

#define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)

sys/dev/drm/i915/i915_reg.h

8157

#define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)

sys/dev/drm/i915/i915_reg.h

8163

#define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)

sys/dev/drm/i915/i915_reg.h

8164

#define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)

sys/dev/drm/i915/i915_reg.h

8183

#define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)

sys/dev/drm/i915/i915_reg.h

8184

#define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)

sys/dev/drm/i915/i915_reg.h

8226

#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)

sys/dev/drm/i915/i915_reg.h

8709

#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \

sys/dev/drm/i915/i915_reg.h

8713

#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \

sys/dev/drm/i915/i915_reg.h

8724

#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)

sys/dev/drm/i915/i915_reg.h

8727

#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)

sys/dev/drm/i915/i915_reg.h

8732

#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)

sys/dev/drm/i915/i915_reg.h

8735

#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)

sys/dev/drm/i915/i915_reg.h

8746

#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)

sys/dev/drm/i915/i915_reg.h

8749

#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)

sys/dev/drm/i915/i915_reg.h

8752

#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)

sys/dev/drm/i915/i915_reg.h

8781

#define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)

sys/dev/drm/i915/i915_reg.h

8785

#define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)

sys/dev/drm/i915/i915_reg.h

8789

#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)

sys/dev/drm/i915/i915_reg.h

8796

#define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)

sys/dev/drm/i915/i915_reg.h

8801

#define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)

sys/dev/drm/i915/i915_reg.h

8806

#define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)

sys/dev/drm/i915/i915_reg.h

9268

#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)

sys/dev/drm/i915/i915_reg.h

965

#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)

sys/dev/drm/i915/i915_reg.h

9652

#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)

sys/dev/drm/i915/i915_reg.h

9709

#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)

sys/dev/drm/i915/i915_reg.h

9710

#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)

sys/dev/drm/i915/i915_reg.h

9711

#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)

sys/dev/drm/i915/i915_reg.h

9712

#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)

sys/dev/drm/i915/i915_reg.h

9713

#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)

sys/dev/drm/i915/i915_reg.h

9714

#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)

sys/dev/drm/i915/i915_reg.h

9715

#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)

sys/dev/drm/i915/i915_reg.h

9716

#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)

sys/dev/drm/i915/i915_reg.h

9717

#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)

sys/dev/drm/i915/i915_reg.h

9718

#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)

sys/dev/drm/i915/i915_reg.h

9719

#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)

sys/dev/drm/i915/i915_reg.h

9720

#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)

sys/dev/drm/i915/i915_reg.h

9721

#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)

sys/dev/drm/i915/i915_reg.h

9744

#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)

sys/dev/drm/i915/i915_reg.h

9745

#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)

sys/dev/drm/i915/i915_reg.h

9746

#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)

sys/dev/drm/i915/i915_reg.h

9747

#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)

sys/dev/drm/i915/i915_reg.h

9757

#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)

sys/dev/drm/i915/i915_reg.h

9758

#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)

sys/dev/drm/i915/i915_reg.h

9782

#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)

sys/dev/drm/i915/i915_reg.h

9783

#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)

sys/dev/drm/i915/i915_reg.h

9784

#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)

sys/dev/drm/i915/i915_reg.h

9785

#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)

sys/dev/drm/i915/i915_reg.h

9786

#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)

sys/dev/drm/i915/i915_reg.h

9787

#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)

sys/dev/drm/i915/i915_reg.h

9788

#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)

sys/dev/drm/i915/i915_reg.h

9789

#define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)

sys/dev/drm/i915/i915_reg.h

9829

#define PIPE_FRMTMSTMP(pipe) \

sys/dev/drm/i915/i915_reg.h

9830

_MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)

sys/dev/drm/i915/intel_atomic.c

307

if (WARN_ON(intel_plane->pipe != intel_crtc->pipe)) {

sys/dev/drm/i915/intel_atomic.c

323

intel_crtc->pipe, *scaler_id, name, idx);

sys/dev/drm/i915/intel_atomic.c

347

} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {

sys/dev/drm/i915/intel_audio.c

323

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_audio.c

335

tmp = I915_READ(HSW_AUD_CFG(pipe));

sys/dev/drm/i915/intel_audio.c

347

I915_WRITE(HSW_AUD_CFG(pipe), tmp);

sys/dev/drm/i915/intel_audio.c

349

tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));

sys/dev/drm/i915/intel_audio.c

360

I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);

sys/dev/drm/i915/intel_audio.c

371

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_audio.c

377

tmp = I915_READ(HSW_AUD_CFG(pipe));

sys/dev/drm/i915/intel_audio.c

394

I915_WRITE(HSW_AUD_CFG(pipe), tmp);

sys/dev/drm/i915/intel_audio.c

400

tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));

sys/dev/drm/i915/intel_audio.c

403

I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);

sys/dev/drm/i915/intel_audio.c

422

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_audio.c

425

DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));

sys/dev/drm/i915/intel_audio.c

430

tmp = I915_READ(HSW_AUD_CFG(pipe));

sys/dev/drm/i915/intel_audio.c

437

I915_WRITE(HSW_AUD_CFG(pipe), tmp);

sys/dev/drm/i915/intel_audio.c

441

tmp &= ~AUDIO_ELD_VALID(pipe);

sys/dev/drm/i915/intel_audio.c

442

tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);

sys/dev/drm/i915/intel_audio.c

455

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_audio.c

461

pipe_name(pipe), drm_eld_size(eld));

sys/dev/drm/i915/intel_audio.c

467

tmp |= AUDIO_OUTPUT_ENABLE(pipe);

sys/dev/drm/i915/intel_audio.c

468

tmp &= ~AUDIO_ELD_VALID(pipe);

sys/dev/drm/i915/intel_audio.c

479

tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));

sys/dev/drm/i915/intel_audio.c

481

I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);

sys/dev/drm/i915/intel_audio.c

486

I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((const u32 *)eld + i));

sys/dev/drm/i915/intel_audio.c

490

tmp |= AUDIO_ELD_VALID(pipe);

sys/dev/drm/i915/intel_audio.c

505

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_audio.c

511

port_name(port), pipe_name(pipe));

sys/dev/drm/i915/intel_audio.c

517

aud_config = IBX_AUD_CFG(pipe);

sys/dev/drm/i915/intel_audio.c

520

aud_config = VLV_AUD_CFG(pipe);

sys/dev/drm/i915/intel_audio.c

523

aud_config = CPT_AUD_CFG(pipe);

sys/dev/drm/i915/intel_audio.c

552

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_audio.c

560

port_name(port), pipe_name(pipe), drm_eld_size(eld));

sys/dev/drm/i915/intel_audio.c

573

hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);

sys/dev/drm/i915/intel_audio.c

574

aud_config = IBX_AUD_CFG(pipe);

sys/dev/drm/i915/intel_audio.c

575

aud_cntl_st = IBX_AUD_CNTL_ST(pipe);

sys/dev/drm/i915/intel_audio.c

579

hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);

sys/dev/drm/i915/intel_audio.c

580

aud_config = VLV_AUD_CFG(pipe);

sys/dev/drm/i915/intel_audio.c

581

aud_cntl_st = VLV_AUD_CNTL_ST(pipe);

sys/dev/drm/i915/intel_audio.c

584

hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);

sys/dev/drm/i915/intel_audio.c

585

aud_config = CPT_AUD_CFG(pipe);

sys/dev/drm/i915/intel_audio.c

586

aud_cntl_st = CPT_AUD_CNTL_ST(pipe);

sys/dev/drm/i915/intel_audio.c

644

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_audio.c

666

dev_priv->av_enc_map[pipe] = encoder;

sys/dev/drm/i915/intel_audio.c

673

pipe = -1;

sys/dev/drm/i915/intel_audio.c

675

(int) port, (int) pipe);

sys/dev/drm/i915/intel_audio.c

678

intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,

sys/dev/drm/i915/intel_audio.c

700

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_audio.c

709

dev_priv->av_enc_map[pipe] = NULL;

sys/dev/drm/i915/intel_audio.c

716

pipe = -1;

sys/dev/drm/i915/intel_audio.c

718

(int) port, (int) pipe);

sys/dev/drm/i915/intel_audio.c

721

intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);

sys/dev/drm/i915/intel_audio.c

808

int port, int pipe)

sys/dev/drm/i915/intel_audio.c

813

if (pipe >= 0) {

sys/dev/drm/i915/intel_audio.c

814

if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))

sys/dev/drm/i915/intel_audio.c

817

encoder = dev_priv->av_enc_map[pipe];

sys/dev/drm/i915/intel_audio.c

829

if (pipe > 0)

sys/dev/drm/i915/intel_audio.c

832

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_audio.c

833

encoder = dev_priv->av_enc_map[pipe];

sys/dev/drm/i915/intel_audio.c

848

int pipe, int rate)

sys/dev/drm/i915/intel_audio.c

863

encoder = get_saved_enc(dev_priv, port, pipe);

sys/dev/drm/i915/intel_audio.c

884

int pipe, bool *enabled,

sys/dev/drm/i915/intel_audio.c

894

intel_encoder = get_saved_enc(dev_priv, port, pipe);

sys/dev/drm/i915/intel_cdclk.c

2227

enum i915_pipe pipe;

sys/dev/drm/i915/intel_cdclk.c

2241

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/intel_cdclk.c

2242

min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);

sys/dev/drm/i915/intel_cdclk.c

2263

enum i915_pipe pipe;

sys/dev/drm/i915/intel_cdclk.c

2277

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/intel_cdclk.c

2278

min_voltage_level = max(state->min_voltage_level[pipe],

sys/dev/drm/i915/intel_color.c

113

int pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_color.c

116

I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);

sys/dev/drm/i915/intel_color.c

117

I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);

sys/dev/drm/i915/intel_color.c

118

I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);

sys/dev/drm/i915/intel_color.c

120

I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU);

sys/dev/drm/i915/intel_color.c

121

I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);

sys/dev/drm/i915/intel_color.c

123

I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);

sys/dev/drm/i915/intel_color.c

124

I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);

sys/dev/drm/i915/intel_color.c

126

I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);

sys/dev/drm/i915/intel_color.c

127

I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);

sys/dev/drm/i915/intel_color.c

129

I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);

sys/dev/drm/i915/intel_color.c

130

I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);

sys/dev/drm/i915/intel_color.c

131

I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);

sys/dev/drm/i915/intel_color.c

132

I915_WRITE(PIPE_CSC_MODE(pipe), 0);

sys/dev/drm/i915/intel_color.c

140

int i, pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_color.c

218

I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]);

sys/dev/drm/i915/intel_color.c

219

I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);

sys/dev/drm/i915/intel_color.c

221

I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]);

sys/dev/drm/i915/intel_color.c

222

I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);

sys/dev/drm/i915/intel_color.c

224

I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]);

sys/dev/drm/i915/intel_color.c

225

I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);

sys/dev/drm/i915/intel_color.c

227

I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);

sys/dev/drm/i915/intel_color.c

228

I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);

sys/dev/drm/i915/intel_color.c

229

I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);

sys/dev/drm/i915/intel_color.c

237

I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);

sys/dev/drm/i915/intel_color.c

238

I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);

sys/dev/drm/i915/intel_color.c

239

I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);

sys/dev/drm/i915/intel_color.c

241

I915_WRITE(PIPE_CSC_MODE(pipe), 0);

sys/dev/drm/i915/intel_color.c

248

I915_WRITE(PIPE_CSC_MODE(pipe), mode);

sys/dev/drm/i915/intel_color.c

260

int pipe = to_intel_crtc(crtc)->pipe;

sys/dev/drm/i915/intel_color.c

284

I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),

sys/dev/drm/i915/intel_color.c

286

I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),

sys/dev/drm/i915/intel_color.c

288

I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),

sys/dev/drm/i915/intel_color.c

290

I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),

sys/dev/drm/i915/intel_color.c

292

I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);

sys/dev/drm/i915/intel_color.c

300

I915_WRITE(CGM_PIPE_MODE(pipe), mode);

sys/dev/drm/i915/intel_color.c

320

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_color.c

327

assert_pll_enabled(dev_priv, pipe);

sys/dev/drm/i915/intel_color.c

339

I915_WRITE(PALETTE(pipe, i), word);

sys/dev/drm/i915/intel_color.c

341

I915_WRITE(LGC_PALETTE(pipe, i), word);

sys/dev/drm/i915/intel_color.c

348

I915_WRITE(PALETTE(pipe, i), word);

sys/dev/drm/i915/intel_color.c

350

I915_WRITE(LGC_PALETTE(pipe, i), word);

sys/dev/drm/i915/intel_color.c

383

I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);

sys/dev/drm/i915/intel_color.c

394

enum i915_pipe pipe = to_intel_crtc(state->crtc)->pipe;

sys/dev/drm/i915/intel_color.c

397

I915_WRITE(PREC_PAL_INDEX(pipe),

sys/dev/drm/i915/intel_color.c

409

I915_WRITE(PREC_PAL_DATA(pipe), word);

sys/dev/drm/i915/intel_color.c

415

I915_WRITE(PREC_PAL_DATA(pipe),

sys/dev/drm/i915/intel_color.c

424

enum i915_pipe pipe = to_intel_crtc(state->crtc)->pipe;

sys/dev/drm/i915/intel_color.c

429

I915_WRITE(PREC_PAL_INDEX(pipe),

sys/dev/drm/i915/intel_color.c

443

I915_WRITE(PREC_PAL_DATA(pipe), word);

sys/dev/drm/i915/intel_color.c

448

I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),

sys/dev/drm/i915/intel_color.c

450

I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),

sys/dev/drm/i915/intel_color.c

452

I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),

sys/dev/drm/i915/intel_color.c

458

I915_WRITE(PREC_PAL_DATA(pipe),

sys/dev/drm/i915/intel_color.c

462

I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);

sys/dev/drm/i915/intel_color.c

463

I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);

sys/dev/drm/i915/intel_color.c

464

I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);

sys/dev/drm/i915/intel_color.c

473

enum i915_pipe pipe = to_intel_crtc(state->crtc)->pipe;

sys/dev/drm/i915/intel_color.c

485

I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);

sys/dev/drm/i915/intel_color.c

486

POSTING_READ(GAMMA_MODE(pipe));

sys/dev/drm/i915/intel_color.c

492

I915_WRITE(PREC_PAL_INDEX(pipe), 0);

sys/dev/drm/i915/intel_color.c

498

enum i915_pipe pipe = to_intel_crtc(state->crtc)->pipe;

sys/dev/drm/i915/intel_color.c

507

I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);

sys/dev/drm/i915/intel_color.c

508

I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);

sys/dev/drm/i915/intel_color.c

517

I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);

sys/dev/drm/i915/intel_color.c

522

I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));

sys/dev/drm/i915/intel_color.c

531

enum i915_pipe pipe = to_intel_crtc(crtc)->pipe;

sys/dev/drm/i915/intel_color.c

543

I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);

sys/dev/drm/i915/intel_color.c

544

POSTING_READ(GAMMA_MODE(pipe));

sys/dev/drm/i915/intel_color.c

552

enum i915_pipe pipe = to_intel_crtc(crtc)->pipe;

sys/dev/drm/i915/intel_color.c

559

I915_WRITE(CGM_PIPE_MODE(pipe),

sys/dev/drm/i915/intel_color.c

576

I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0);

sys/dev/drm/i915/intel_color.c

577

I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1);

sys/dev/drm/i915/intel_color.c

591

I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0);

sys/dev/drm/i915/intel_color.c

592

I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1);

sys/dev/drm/i915/intel_color.c

596

I915_WRITE(CGM_PIPE_MODE(pipe),

sys/dev/drm/i915/intel_crt.c

173

adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);

sys/dev/drm/i915/intel_crt.c

175

adpa |= ADPA_PIPE_SEL(crtc->pipe);

sys/dev/drm/i915/intel_crt.c

178

I915_WRITE(BCLRPAT(crtc->pipe), 0);

sys/dev/drm/i915/intel_crt.c

266

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_crt.c

270

intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);

sys/dev/drm/i915/intel_crt.c

283

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_crt.c

289

intel_wait_for_vblank(dev_priv, pipe);

sys/dev/drm/i915/intel_crt.c

290

intel_wait_for_vblank(dev_priv, pipe);

sys/dev/drm/i915/intel_crt.c

291

intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

sys/dev/drm/i915/intel_crt.c

629

intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)

sys/dev/drm/i915/intel_crt.c

646

bclrpat_reg = BCLRPAT(pipe);

sys/dev/drm/i915/intel_crt.c

647

vtotal_reg = VTOTAL(pipe);

sys/dev/drm/i915/intel_crt.c

648

vblank_reg = VBLANK(pipe);

sys/dev/drm/i915/intel_crt.c

649

vsync_reg = VSYNC(pipe);

sys/dev/drm/i915/intel_crt.c

650

pipeconf_reg = PIPECONF(pipe);

sys/dev/drm/i915/intel_crt.c

651

pipe_dsl_reg = PIPEDSL(pipe);

sys/dev/drm/i915/intel_crt.c

67

i915_reg_t adpa_reg, enum i915_pipe *pipe)

sys/dev/drm/i915/intel_crt.c

672

intel_wait_for_vblank(dev_priv, pipe);

sys/dev/drm/i915/intel_crt.c

75

*pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;

sys/dev/drm/i915/intel_crt.c

77

*pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;

sys/dev/drm/i915/intel_crt.c

83

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_crt.c

835

to_intel_crtc(connector->state->crtc)->pipe);

sys/dev/drm/i915/intel_crt.c

93

ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);

sys/dev/drm/i915/intel_ddi.c

1264

pipe_name(crtc->pipe));

sys/dev/drm/i915/intel_ddi.c

1811

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_ddi.c

1843

switch (pipe) {

sys/dev/drm/i915/intel_ddi.c

1917

enum i915_pipe pipe = 0;

sys/dev/drm/i915/intel_ddi.c

1925

if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {

sys/dev/drm/i915/intel_ddi.c

1930

tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));

sys/dev/drm/i915/intel_ddi.c

1935

I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);

sys/dev/drm/i915/intel_ddi.c

1948

enum i915_pipe pipe = 0;

sys/dev/drm/i915/intel_ddi.c

1957

if (!encoder->get_hw_state(encoder, &pipe)) {

sys/dev/drm/i915/intel_ddi.c

1965

cpu_transcoder = (enum transcoder) pipe;

sys/dev/drm/i915/intel_ddi.c

2002

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_ddi.c

2028

*pipe = PIPE_A;

sys/dev/drm/i915/intel_ddi.c

2031

*pipe = PIPE_B;

sys/dev/drm/i915/intel_ddi.c

2034

*pipe = PIPE_C;

sys/dev/drm/i915/intel_ddi.c

2053

*pipe = p;

sys/dev/drm/i915/intel_ddi.c

2977

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_ddi.c

2994

intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

sys/dev/drm/i915/intel_device_info.c

742

enum i915_pipe pipe;

sys/dev/drm/i915/intel_device_info.c

745

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/intel_device_info.c

746

info->num_scalers[pipe] = 2;

sys/dev/drm/i915/intel_device_info.c

765

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/intel_device_info.c

766

info->num_sprites[pipe] = 3;

sys/dev/drm/i915/intel_device_info.c

772

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/intel_device_info.c

773

info->num_sprites[pipe] = 2;

sys/dev/drm/i915/intel_device_info.c

775

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/intel_device_info.c

776

info->num_sprites[pipe] = 1;

sys/dev/drm/i915/intel_display.c

10033

cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);

sys/dev/drm/i915/intel_display.c

10100

enum i915_pipe pipe = plane->pipe;

sys/dev/drm/i915/intel_display.c

10138

if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&

sys/dev/drm/i915/intel_display.c

10154

enum i915_pipe pipe = plane->pipe;

sys/dev/drm/i915/intel_display.c

10191

I915_WRITE_FW(CURCNTR(pipe), cntl);

sys/dev/drm/i915/intel_display.c

10193

I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl);

sys/dev/drm/i915/intel_display.c

10194

I915_WRITE_FW(CURPOS(pipe), pos);

sys/dev/drm/i915/intel_display.c

10195

I915_WRITE_FW(CURBASE(pipe), base);

sys/dev/drm/i915/intel_display.c

10201

I915_WRITE_FW(CURPOS(pipe), pos);

sys/dev/drm/i915/intel_display.c

10202

I915_WRITE_FW(CURBASE(pipe), base);

sys/dev/drm/i915/intel_display.c

10205

POSTING_READ_FW(CURBASE(pipe));

sys/dev/drm/i915/intel_display.c

10217

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_display.c

10229

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/drm/i915/intel_display.c

10233

val = I915_READ(CURCNTR(plane->pipe));

sys/dev/drm/i915/intel_display.c

10238

*pipe = plane->pipe;

sys/dev/drm/i915/intel_display.c

10240

*pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>

sys/dev/drm/i915/intel_display.c

1038

enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

1040

struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

10440

intel_wait_for_vblank(dev_priv, intel_crtc->pipe);

sys/dev/drm/i915/intel_display.c

1046

enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

1048

i915_reg_t reg = PIPEDSL(pipe);

sys/dev/drm/i915/intel_display.c

10504

int pipe = pipe_config->cpu_transcoder;

sys/dev/drm/i915/intel_display.c

10554

bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);

sys/dev/drm/i915/intel_display.c

10633

enum i915_pipe pipe;

sys/dev/drm/i915/intel_display.c

10635

if (!encoder->get_hw_state(encoder, &pipe))

sys/dev/drm/i915/intel_display.c

10638

crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1067

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

1070

if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100))

sys/dev/drm/i915/intel_display.c

1072

pipe_name(pipe), onoff(state));

sys/dev/drm/i915/intel_display.c

1107

enum i915_pipe pipe, bool state)

sys/dev/drm/i915/intel_display.c

1112

val = I915_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

11177

if (intel_plane->pipe != crtc->pipe)

sys/dev/drm/i915/intel_display.c

11324

(enum transcoder) to_intel_crtc(crtc)->pipe;

sys/dev/drm/i915/intel_display.c

1136

enum i915_pipe pipe, bool state)

sys/dev/drm/i915/intel_display.c

1140

pipe);

sys/dev/drm/i915/intel_display.c

1147

u32 val = I915_READ(FDI_TX_CTL(pipe));

sys/dev/drm/i915/intel_display.c

1158

enum i915_pipe pipe, bool state)

sys/dev/drm/i915/intel_display.c

1163

val = I915_READ(FDI_RX_CTL(pipe));

sys/dev/drm/i915/intel_display.c

1173

enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

11839

const enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

1185

val = I915_READ(FDI_TX_CTL(pipe));

sys/dev/drm/i915/intel_display.c

11857

for_each_universal_plane(dev_priv, pipe, plane) {

sys/dev/drm/i915/intel_display.c

11868

pipe_name(pipe), plane + 1, level,

sys/dev/drm/i915/intel_display.c

11880

pipe_name(pipe), plane + 1,

sys/dev/drm/i915/intel_display.c

11890

hw_ddb_entry = &hw_ddb.plane[pipe][plane];

sys/dev/drm/i915/intel_display.c

11891

sw_ddb_entry = &sw_ddb->plane[pipe][plane];

sys/dev/drm/i915/intel_display.c

11895

pipe_name(pipe), plane + 1,

sys/dev/drm/i915/intel_display.c

1190

enum i915_pipe pipe, bool state)

sys/dev/drm/i915/intel_display.c

11918

pipe_name(pipe), level,

sys/dev/drm/i915/intel_display.c

11930

pipe_name(pipe),

sys/dev/drm/i915/intel_display.c

11940

hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];

sys/dev/drm/i915/intel_display.c

11941

sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];

sys/dev/drm/i915/intel_display.c

11945

pipe_name(pipe),

sys/dev/drm/i915/intel_display.c

1195

val = I915_READ(FDI_RX_CTL(pipe));

sys/dev/drm/i915/intel_display.c

11988

enum i915_pipe pipe;

sys/dev/drm/i915/intel_display.c

12019

active = encoder->get_hw_state(encoder, &pipe);

sys/dev/drm/i915/intel_display.c

1202

void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

12022

pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

12064

enum i915_pipe pipe;

sys/dev/drm/i915/intel_display.c

12066

active = encoder->get_hw_state(encoder, &pipe);

sys/dev/drm/i915/intel_display.c

12071

I915_STATE_WARN(active && intel_crtc->pipe != pipe,

sys/dev/drm/i915/intel_display.c

12073

pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

12328

first_pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

12354

enabled_pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

1237

pp_reg = PP_CONTROL(pipe);

sys/dev/drm/i915/intel_display.c

1238

panel_pipe = pipe;

sys/dev/drm/i915/intel_display.c

1254

I915_STATE_WARN(panel_pipe == pipe && locked,

sys/dev/drm/i915/intel_display.c

1256

pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

1260

enum i915_pipe pipe, bool state)

sys/dev/drm/i915/intel_display.c

12601

return dev->driver->get_vblank_counter(dev, crtc->pipe);

sys/dev/drm/i915/intel_display.c

1264

pipe);

sys/dev/drm/i915/intel_display.c

12660

enum i915_pipe pipe;

sys/dev/drm/i915/intel_display.c

12691

pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

12721

intel_wait_for_vblank(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

12811

put_domains[to_intel_crtc(crtc)->pipe] =

sys/dev/drm/i915/intel_display.c

1283

pipe_name(pipe), onoff(state), onoff(cur_state));

sys/dev/drm/i915/intel_display.c

1288

enum i915_pipe pipe;

sys/dev/drm/i915/intel_display.c

1291

cur_state = plane->get_hw_state(plane, &pipe);

sys/dev/drm/i915/intel_display.c

1317

enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

1322

val = I915_READ(PCH_TRANSCONF(pipe));

sys/dev/drm/i915/intel_display.c

1326

pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

1330

enum i915_pipe pipe, enum port port,

sys/dev/drm/i915/intel_display.c

1338

I915_STATE_WARN(state && port_pipe == pipe,

sys/dev/drm/i915/intel_display.c

1340

port_name(port), pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

13445

intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);

sys/dev/drm/i915/intel_display.c

1348

enum i915_pipe pipe, enum port port,

sys/dev/drm/i915/intel_display.c

1356

I915_STATE_WARN(state && port_pipe == pipe,

sys/dev/drm/i915/intel_display.c

1358

port_name(port), pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

1366

enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

1370

assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);

sys/dev/drm/i915/intel_display.c

1371

assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C);

sys/dev/drm/i915/intel_display.c

1372

assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);

sys/dev/drm/i915/intel_display.c

1375

port_pipe == pipe,

sys/dev/drm/i915/intel_display.c

13766

enum i915_pipe pipe, enum plane_id plane_id)

sys/dev/drm/i915/intel_display.c

1377

pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

13771

return pipe == PIPE_A && plane_id == PLANE_PRIMARY;

sys/dev/drm/i915/intel_display.c

13775

enum i915_pipe pipe, enum plane_id plane_id)

sys/dev/drm/i915/intel_display.c

13787

if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C)

sys/dev/drm/i915/intel_display.c

13797

intel_primary_plane_create(struct drm_i915_private *dev_priv, enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

1380

port_pipe == pipe,

sys/dev/drm/i915/intel_display.c

1382

pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

13824

primary->pipe = pipe;

sys/dev/drm/i915/intel_display.c

13830

primary->i9xx_plane = (enum i9xx_plane_id) !pipe;

sys/dev/drm/i915/intel_display.c

13832

primary->i9xx_plane = (enum i9xx_plane_id) pipe;

sys/dev/drm/i915/intel_display.c

13834

primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);

sys/dev/drm/i915/intel_display.c

13838

primary->pipe,

sys/dev/drm/i915/intel_display.c

1384

assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);

sys/dev/drm/i915/intel_display.c

1385

assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);

sys/dev/drm/i915/intel_display.c

13851

primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,

sys/dev/drm/i915/intel_display.c

13854

if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {

sys/dev/drm/i915/intel_display.c

1386

assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);

sys/dev/drm/i915/intel_display.c

13906

"plane 1%c", pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

13913

"primary %c", pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

1393

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

13934

} else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {

sys/dev/drm/i915/intel_display.c

1395

I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);

sys/dev/drm/i915/intel_display.c

1396

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

13972

enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

13992

cursor->pipe = pipe;

sys/dev/drm/i915/intel_display.c

13993

cursor->i9xx_plane = (enum i9xx_plane_id) pipe;

sys/dev/drm/i915/intel_display.c

13995

cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);

sys/dev/drm/i915/intel_display.c

1400

DPLL(pipe),

sys/dev/drm/i915/intel_display.c

14023

"cursor %c", pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

1404

DRM_ERROR("DPLL %d failed to lock\n", pipe);

sys/dev/drm/i915/intel_display.c

14055

crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];

sys/dev/drm/i915/intel_display.c

14069

static int intel_crtc_init(struct drm_i915_private *dev_priv, enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

14090

primary = intel_primary_plane_create(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

14097

for_each_sprite(dev_priv, pipe, sprite) {

sys/dev/drm/i915/intel_display.c

14100

plane = intel_sprite_plane_create(dev_priv, pipe, sprite);

sys/dev/drm/i915/intel_display.c

14108

cursor = intel_cursor_plane_create(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1411

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

14118

"pipe %c", pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

14122

intel_crtc->pipe = pipe;

sys/dev/drm/i915/intel_display.c

14127

BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||

sys/dev/drm/i915/intel_display.c

14128

dev_priv->pipe_to_crtc_mapping[pipe] != NULL);

sys/dev/drm/i915/intel_display.c

14129

dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc;

sys/dev/drm/i915/intel_display.c

1413

assert_pipe_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

14143

WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);

sys/dev/drm/i915/intel_display.c

1416

assert_panel_unlocked(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

14167

return to_intel_crtc(connector->base.state->crtc)->pipe;

sys/dev/drm/i915/intel_display.c

14182

pipe_from_crtc_id->pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

1421

I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);

sys/dev/drm/i915/intel_display.c

1422

POSTING_READ(DPLL_MD(pipe));

sys/dev/drm/i915/intel_display.c

1430

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

1431

enum dpio_channel port = vlv_pipe_to_channel(pipe);

sys/dev/drm/i915/intel_display.c

1437

tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));

sys/dev/drm/i915/intel_display.c

1439

vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);

sys/dev/drm/i915/intel_display.c

1449

I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);

sys/dev/drm/i915/intel_display.c

1453

DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,

sys/dev/drm/i915/intel_display.c

1455

DRM_ERROR("PLL %d failed to lock\n", pipe);

sys/dev/drm/i915/intel_display.c

1462

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

1464

assert_pipe_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1467

assert_panel_unlocked(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1472

if (pipe != PIPE_A) {

sys/dev/drm/i915/intel_display.c

1479

I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));

sys/dev/drm/i915/intel_display.c

1482

dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;

sys/dev/drm/i915/intel_display.c

1490

I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);

sys/dev/drm/i915/intel_display.c

1491

POSTING_READ(DPLL_MD(pipe));

sys/dev/drm/i915/intel_display.c

1512

i915_reg_t reg = DPLL(crtc->pipe);

sys/dev/drm/i915/intel_display.c

1516

assert_pipe_disabled(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_display.c

1520

assert_panel_unlocked(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_display.c

1531

I915_WRITE(DPLL(!crtc->pipe),

sys/dev/drm/i915/intel_display.c

1532

I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);

sys/dev/drm/i915/intel_display.c

15336

enum i915_pipe pipe;

sys/dev/drm/i915/intel_display.c

15409

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_display.c

15410

ret = intel_crtc_init(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

15478

void i830_enable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

15480

struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1549

I915_WRITE(DPLL_MD(crtc->pipe),

sys/dev/drm/i915/intel_display.c

15495

pipe_name(pipe), clock.vco, clock.dot);

sys/dev/drm/i915/intel_display.c

15498

dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |

sys/dev/drm/i915/intel_display.c

15505

I915_WRITE(FP0(pipe), fp);

sys/dev/drm/i915/intel_display.c

15506

I915_WRITE(FP1(pipe), fp);

sys/dev/drm/i915/intel_display.c

15508

I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));

sys/dev/drm/i915/intel_display.c

15509

I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));

sys/dev/drm/i915/intel_display.c

15510

I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));

sys/dev/drm/i915/intel_display.c

15511

I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));

sys/dev/drm/i915/intel_display.c

15512

I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));

sys/dev/drm/i915/intel_display.c

15513

I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));

sys/dev/drm/i915/intel_display.c

15514

I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));

sys/dev/drm/i915/intel_display.c

15521

I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);

sys/dev/drm/i915/intel_display.c

15522

I915_WRITE(DPLL(pipe), dpll);

sys/dev/drm/i915/intel_display.c

15525

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

15533

I915_WRITE(DPLL(pipe), dpll);

sys/dev/drm/i915/intel_display.c

15537

I915_WRITE(DPLL(pipe), dpll);

sys/dev/drm/i915/intel_display.c

15538

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

15542

I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);

sys/dev/drm/i915/intel_display.c

15543

POSTING_READ(PIPECONF(pipe));

sys/dev/drm/i915/intel_display.c

15548

void i830_disable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

15550

struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

15553

pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

15561

I915_WRITE(PIPECONF(pipe), 0);

sys/dev/drm/i915/intel_display.c

15562

POSTING_READ(PIPECONF(pipe));

sys/dev/drm/i915/intel_display.c

15566

I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);

sys/dev/drm/i915/intel_display.c

15567

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

15582

enum i915_pipe pipe;

sys/dev/drm/i915/intel_display.c

15584

if (!plane->get_hw_state(plane, &pipe))

sys/dev/drm/i915/intel_display.c

15587

if (pipe == crtc->pipe)

sys/dev/drm/i915/intel_display.c

15593

plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

15685

if (has_pch_trancoder(dev_priv, crtc->pipe))

sys/dev/drm/i915/intel_display.c

1571

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

15725

pipe_name(crtc->pipe));

sys/dev/drm/i915/intel_display.c

15810

enum i915_pipe pipe = PIPE_A;

sys/dev/drm/i915/intel_display.c

15813

visible = plane->get_hw_state(plane, &pipe);

sys/dev/drm/i915/intel_display.c

15815

crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

15832

enum i915_pipe pipe;

sys/dev/drm/i915/intel_display.c

15856

dev_priv->active_crtcs |= 1 << crtc->pipe;

sys/dev/drm/i915/intel_display.c

15877

pll->state.crtc_mask |= 1 << crtc->pipe;

sys/dev/drm/i915/intel_display.c

1588

assert_pipe_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

15886

pipe = 0;

sys/dev/drm/i915/intel_display.c

15888

if (encoder->get_hw_state(encoder, &pipe)) {

sys/dev/drm/i915/intel_display.c

15891

crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1590

I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);

sys/dev/drm/i915/intel_display.c

15903

pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

1591

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

1594

static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

15974

dev_priv->min_cdclk[crtc->pipe] = min_cdclk;

sys/dev/drm/i915/intel_display.c

15975

dev_priv->min_voltage_level[crtc->pipe] =

sys/dev/drm/i915/intel_display.c

1599

assert_pipe_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1603

if (pipe != PIPE_A)

sys/dev/drm/i915/intel_display.c

1606

I915_WRITE(DPLL(pipe), val);

sys/dev/drm/i915/intel_display.c

1607

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

1610

static void chv_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

1612

enum dpio_channel port = vlv_pipe_to_channel(pipe);

sys/dev/drm/i915/intel_display.c

1616

assert_pipe_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1620

if (pipe != PIPE_A)

sys/dev/drm/i915/intel_display.c

1623

I915_WRITE(DPLL(pipe), val);

sys/dev/drm/i915/intel_display.c

1624

POSTING_READ(DPLL(pipe));

sys/dev/drm/i915/intel_display.c

16279

} pipe[I915_MAX_PIPES];

sys/dev/drm/i915/intel_display.c

1629

val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));

sys/dev/drm/i915/intel_display.c

1631

vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);

sys/dev/drm/i915/intel_display.c

16329

error->pipe[i].power_domain_on =

sys/dev/drm/i915/intel_display.c

16332

if (!error->pipe[i].power_domain_on)

sys/dev/drm/i915/intel_display.c

16352

error->pipe[i].source = I915_READ(PIPESRC(i));

sys/dev/drm/i915/intel_display.c

16355

error->pipe[i].stat = I915_READ(PIPESTAT(i));

sys/dev/drm/i915/intel_display.c

16405

onoff(error->pipe[i].power_domain_on));

sys/dev/drm/i915/intel_display.c

16406

err_printf(m, " SRC: %08x\n", error->pipe[i].source);

sys/dev/drm/i915/intel_display.c

16407

err_printf(m, " STAT: %08x\n", error->pipe[i].stat);

sys/dev/drm/i915/intel_display.c

1670

enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

1673

pipe);

sys/dev/drm/i915/intel_display.c

1681

assert_fdi_tx_enabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1682

assert_fdi_rx_enabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1687

reg = TRANS_CHICKEN2(pipe);

sys/dev/drm/i915/intel_display.c

1693

reg = PCH_TRANSCONF(pipe);

sys/dev/drm/i915/intel_display.c

1695

pipeconf_val = I915_READ(PIPECONF(pipe));

sys/dev/drm/i915/intel_display.c

1724

DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

1760

enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

1766

assert_fdi_tx_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1767

assert_fdi_rx_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1770

assert_pch_ports_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1772

reg = PCH_TRANSCONF(pipe);

sys/dev/drm/i915/intel_display.c

1780

DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

1784

reg = TRANS_CHICKEN2(pipe);

sys/dev/drm/i915/intel_display.c

1817

return crtc->pipe;

sys/dev/drm/i915/intel_display.c

1825

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

1829

DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

1842

assert_pll_enabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

1881

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

1885

DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

2908

intel_crtc->pipe, PTR_ERR(intel_state->vma));

sys/dev/drm/i915/intel_display.c

3272

dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);

sys/dev/drm/i915/intel_display.c

3477

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_display.c

3490

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/drm/i915/intel_display.c

3499

*pipe = plane->pipe;

sys/dev/drm/i915/intel_display.c

3501

*pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>

sys/dev/drm/i915/intel_display.c

3523

I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);

sys/dev/drm/i915/intel_display.c

3524

I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);

sys/dev/drm/i915/intel_display.c

3525

I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);

sys/dev/drm/i915/intel_display.c

3930

I915_WRITE(PIPESRC(crtc->pipe),

sys/dev/drm/i915/intel_display.c

3952

int pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

3957

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

3968

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

3995

int pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

4000

assert_pipe_enabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

4004

reg = FDI_RX_IMR(pipe);

sys/dev/drm/i915/intel_display.c

4013

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4021

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4031

I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);

sys/dev/drm/i915/intel_display.c

4032

I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |

sys/dev/drm/i915/intel_display.c

4035

reg = FDI_RX_IIR(pipe);

sys/dev/drm/i915/intel_display.c

4050

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4056

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4065

reg = FDI_RX_IIR(pipe);

sys/dev/drm/i915/intel_display.c

4096

int pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

4102

reg = FDI_RX_IMR(pipe);

sys/dev/drm/i915/intel_display.c

4112

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4123

I915_WRITE(FDI_RX_MISC(pipe),

sys/dev/drm/i915/intel_display.c

4126

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4141

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4151

reg = FDI_RX_IIR(pipe);

sys/dev/drm/i915/intel_display.c

4168

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4179

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4194

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4204

reg = FDI_RX_IIR(pipe);

sys/dev/drm/i915/intel_display.c

4229

int pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

4235

reg = FDI_RX_IMR(pipe);

sys/dev/drm/i915/intel_display.c

4245

I915_READ(FDI_RX_IIR(pipe)));

sys/dev/drm/i915/intel_display.c

4250

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4256

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4264

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4274

I915_WRITE(FDI_RX_MISC(pipe),

sys/dev/drm/i915/intel_display.c

4277

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4287

reg = FDI_RX_IIR(pipe);

sys/dev/drm/i915/intel_display.c

4306

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4312

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4322

reg = FDI_RX_IIR(pipe);

sys/dev/drm/i915/intel_display.c

4347

int pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

4352

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4356

temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;

sys/dev/drm/i915/intel_display.c

4370

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4384

int pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

4389

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4394

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4401

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4415

int pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

4420

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4425

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4428

temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;

sys/dev/drm/i915/intel_display.c

4436

I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);

sys/dev/drm/i915/intel_display.c

4439

reg = FDI_TX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4445

reg = FDI_RX_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4456

temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;

sys/dev/drm/i915/intel_display.c

4667

switch (intel_crtc->pipe) {

sys/dev/drm/i915/intel_display.c

4710

num_encoders, pipe_name(crtc->pipe));

sys/dev/drm/i915/intel_display.c

4729

int pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

4732

assert_pch_transcoder_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

4739

I915_WRITE(FDI_RX_TUSIZE1(pipe),

sys/dev/drm/i915/intel_display.c

4740

I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);

sys/dev/drm/i915/intel_display.c

4751

temp |= TRANS_DPLL_ENABLE(pipe);

sys/dev/drm/i915/intel_display.c

4752

sel = TRANS_DPLLB_SEL(pipe);

sys/dev/drm/i915/intel_display.c

4771

assert_panel_unlocked(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

4772

ironlake_pch_transcoder_set_timings(crtc, pipe);

sys/dev/drm/i915/intel_display.c

4781

u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;

sys/dev/drm/i915/intel_display.c

4782

i915_reg_t reg = TRANS_DP_CTL(pipe);

sys/dev/drm/i915/intel_display.c

4804

ironlake_enable_pch_transcoder(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

4824

static void cpt_verify_modeset(struct drm_device *dev, int pipe)

sys/dev/drm/i915/intel_display.c

4827

i915_reg_t dslreg = PIPEDSL(pipe);

sys/dev/drm/i915/intel_display.c

4834

DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));

sys/dev/drm/i915/intel_display.c

4962

intel_crtc->pipe, scaler_user, *scaler_id,

sys/dev/drm/i915/intel_display.c

4986

intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);

sys/dev/drm/i915/intel_display.c

4994

intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,

sys/dev/drm/i915/intel_display.c

509

skl_wa_528(struct drm_i915_private *dev_priv, int pipe, bool enable)

sys/dev/drm/i915/intel_display.c

5097

int pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

5119

I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |

sys/dev/drm/i915/intel_display.c

5121

I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),

sys/dev/drm/i915/intel_display.c

5123

I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),

sys/dev/drm/i915/intel_display.c

5125

I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);

sys/dev/drm/i915/intel_display.c

5126

I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);

sys/dev/drm/i915/intel_display.c

5134

int pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

5142

I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |

sys/dev/drm/i915/intel_display.c

5143

PF_PIPE_SEL_IVB(pipe));

sys/dev/drm/i915/intel_display.c

5145

I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);

sys/dev/drm/i915/intel_display.c

5146

I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);

sys/dev/drm/i915/intel_display.c

5147

I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);

sys/dev/drm/i915/intel_display.c

515

I915_WRITE(CHICKEN_PIPESL_1(pipe), HSW_FBCQ_DIS);

sys/dev/drm/i915/intel_display.c

517

I915_WRITE(CHICKEN_PIPESL_1(pipe), 0);

sys/dev/drm/i915/intel_display.c

521

skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable)

sys/dev/drm/i915/intel_display.c

5219

intel_wait_for_vblank(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_display.c

5255

int pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

5265

intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

sys/dev/drm/i915/intel_display.c

527

I915_WRITE(CLKGATE_DIS_PSL(pipe),

sys/dev/drm/i915/intel_display.c

5279

int pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

5286

intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);

sys/dev/drm/i915/intel_display.c

530

I915_WRITE(CLKGATE_DIS_PSL(pipe),

sys/dev/drm/i915/intel_display.c

5301

intel_wait_for_vblank(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

531

I915_READ(CLKGATE_DIS_PSL(pipe)) &

sys/dev/drm/i915/intel_display.c

5388

skl_wa_clkgate(dev_priv, crtc->pipe, false);

sys/dev/drm/i915/intel_display.c

5389

skl_wa_528(dev_priv, crtc->pipe, false);

sys/dev/drm/i915/intel_display.c

5422

intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);

sys/dev/drm/i915/intel_display.c

5428

skl_wa_clkgate(dev_priv, crtc->pipe, true);

sys/dev/drm/i915/intel_display.c

5429

skl_wa_528(dev_priv, crtc->pipe, true);

sys/dev/drm/i915/intel_display.c

5443

intel_wait_for_vblank(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_display.c

5453

intel_wait_for_vblank(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_display.c

5488

int pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

5500

intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));

sys/dev/drm/i915/intel_display.c

5630

int pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

5647

intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);

sys/dev/drm/i915/intel_display.c

5648

intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);

sys/dev/drm/i915/intel_display.c

5676

assert_fdi_tx_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

5677

assert_fdi_rx_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

5701

cpt_verify_modeset(dev, intel_crtc->pipe);

sys/dev/drm/i915/intel_display.c

5710

intel_wait_for_vblank(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

5711

intel_wait_for_vblank(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

5713

intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

sys/dev/drm/i915/intel_display.c

5714

intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);

sys/dev/drm/i915/intel_display.c

5720

return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;

sys/dev/drm/i915/intel_display.c

5724

enum i915_pipe pipe, bool apply)

sys/dev/drm/i915/intel_display.c

5726

u32 val = I915_READ(CLKGATE_DIS_PSL(pipe));

sys/dev/drm/i915/intel_display.c

5734

I915_WRITE(CLKGATE_DIS_PSL(pipe), val);

sys/dev/drm/i915/intel_display.c

5740

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

5748

I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);

sys/dev/drm/i915/intel_display.c

5757

int pipe = intel_crtc->pipe, hsw_workaround_pipe;

sys/dev/drm/i915/intel_display.c

5809

glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);

sys/dev/drm/i915/intel_display.c

5827

pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));

sys/dev/drm/i915/intel_display.c

5829

I915_WRITE_FW(PIPE_CHICKEN(pipe),

sys/dev/drm/i915/intel_display.c

5859

intel_wait_for_vblank(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

5860

glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);

sys/dev/drm/i915/intel_display.c

5876

int pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

5881

I915_WRITE(PF_CTL(pipe), 0);

sys/dev/drm/i915/intel_display.c

5882

I915_WRITE(PF_WIN_POS(pipe), 0);

sys/dev/drm/i915/intel_display.c

5883

I915_WRITE(PF_WIN_SZ(pipe), 0);

sys/dev/drm/i915/intel_display.c

5894

int pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

5901

intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);

sys/dev/drm/i915/intel_display.c

5902

intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);

sys/dev/drm/i915/intel_display.c

5919

ironlake_disable_pch_transcoder(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

5926

reg = TRANS_DP_CTL(pipe);

sys/dev/drm/i915/intel_display.c

5935

temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));

sys/dev/drm/i915/intel_display.c

5942

intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

sys/dev/drm/i915/intel_display.c

5943

intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);

sys/dev/drm/i915/intel_display.c

5994

assert_pipe_disabled(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_display.c

6001

I915_WRITE(BCLRPAT(crtc->pipe), 0);

sys/dev/drm/i915/intel_display.c

6059

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

6066

mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));

sys/dev/drm/i915/intel_display.c

6070

mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));

sys/dev/drm/i915/intel_display.c

6126

int pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

6137

if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {

sys/dev/drm/i915/intel_display.c

6140

I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);

sys/dev/drm/i915/intel_display.c

6141

I915_WRITE(CHV_CANVAS(pipe), 0);

sys/dev/drm/i915/intel_display.c

6150

intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

sys/dev/drm/i915/intel_display.c

6183

I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);

sys/dev/drm/i915/intel_display.c

6184

I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);

sys/dev/drm/i915/intel_display.c

6196

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

6214

intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

sys/dev/drm/i915/intel_display.c

6245

assert_pipe_disabled(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_display.c

6259

int pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

6266

intel_wait_for_vblank(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

6281

chv_disable_pll(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

6283

vlv_disable_pll(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

6291

intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);

sys/dev/drm/i915/intel_display.c

6298

i830_enable_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

6366

dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);

sys/dev/drm/i915/intel_display.c

6367

dev_priv->min_cdclk[intel_crtc->pipe] = 0;

sys/dev/drm/i915/intel_display.c

6368

dev_priv->min_voltage_level[intel_crtc->pipe] = 0;

sys/dev/drm/i915/intel_display.c

6491

enum i915_pipe pipe = 0;

sys/dev/drm/i915/intel_display.c

6494

return encoder->get_hw_state(encoder, &pipe);

sys/dev/drm/i915/intel_display.c

6505

static int ironlake_check_fdi_lanes(struct drm_device *dev, enum i915_pipe pipe,

sys/dev/drm/i915/intel_display.c

6514

pipe_name(pipe), pipe_config->fdi_lanes);

sys/dev/drm/i915/intel_display.c

6517

pipe_name(pipe), pipe_config->fdi_lanes);

sys/dev/drm/i915/intel_display.c

6535

switch (pipe) {

sys/dev/drm/i915/intel_display.c

6550

pipe_name(pipe), pipe_config->fdi_lanes);

sys/dev/drm/i915/intel_display.c

6557

pipe_name(pipe), pipe_config->fdi_lanes);

sys/dev/drm/i915/intel_display.c

6606

ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);

sys/dev/drm/i915/intel_display.c

6683

(crtc->pipe == PIPE_A || IS_I915G(dev_priv));

sys/dev/drm/i915/intel_display.c

6901

pipe)

sys/dev/drm/i915/intel_display.c

6909

reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));

sys/dev/drm/i915/intel_display.c

6912

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);

sys/dev/drm/i915/intel_display.c

6914

reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);

sys/dev/drm/i915/intel_display.c

6917

vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);

sys/dev/drm/i915/intel_display.c

6919

reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));

sys/dev/drm/i915/intel_display.c

6921

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);

sys/dev/drm/i915/intel_display.c

6923

reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);

sys/dev/drm/i915/intel_display.c

6926

vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);

sys/dev/drm/i915/intel_display.c

6934

int pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

6936

I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);

sys/dev/drm/i915/intel_display.c

6937

I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);

sys/dev/drm/i915/intel_display.c

6938

I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);

sys/dev/drm/i915/intel_display.c

6939

I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);

sys/dev/drm/i915/intel_display.c

6947

int pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

6968

I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);

sys/dev/drm/i915/intel_display.c

6969

I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);

sys/dev/drm/i915/intel_display.c

6970

I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);

sys/dev/drm/i915/intel_display.c

6971

I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);

sys/dev/drm/i915/intel_display.c

7005

if (crtc->pipe != PIPE_A)

sys/dev/drm/i915/intel_display.c

7022

if (crtc->pipe != PIPE_A)

sys/dev/drm/i915/intel_display.c

7038

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

7044

I915_WRITE(DPLL(pipe),

sys/dev/drm/i915/intel_display.c

7063

if (pipe == PIPE_B)

sys/dev/drm/i915/intel_display.c

7064

vlv_pllb_recal_opamp(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

7067

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);

sys/dev/drm/i915/intel_display.c

7070

reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));

sys/dev/drm/i915/intel_display.c

7072

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);

sys/dev/drm/i915/intel_display.c

7075

vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);

sys/dev/drm/i915/intel_display.c

7089

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);

sys/dev/drm/i915/intel_display.c

7092

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);

sys/dev/drm/i915/intel_display.c

7098

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),

sys/dev/drm/i915/intel_display.c

7101

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),

sys/dev/drm/i915/intel_display.c

7106

if (pipe == PIPE_A)

sys/dev/drm/i915/intel_display.c

7107

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),

sys/dev/drm/i915/intel_display.c

7110

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),

sys/dev/drm/i915/intel_display.c

7114

if (pipe == PIPE_A)

sys/dev/drm/i915/intel_display.c

7115

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),

sys/dev/drm/i915/intel_display.c

7118

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),

sys/dev/drm/i915/intel_display.c

7122

coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));

sys/dev/drm/i915/intel_display.c

7126

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);

sys/dev/drm/i915/intel_display.c

7128

vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);

sys/dev/drm/i915/intel_display.c

7137

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

7138

enum dpio_channel port = vlv_pipe_to_channel(pipe);

sys/dev/drm/i915/intel_display.c

7145

I915_WRITE(DPLL(pipe),

sys/dev/drm/i915/intel_display.c

7165

vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),

sys/dev/drm/i915/intel_display.c

7172

vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);

sys/dev/drm/i915/intel_display.c

7175

vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),

sys/dev/drm/i915/intel_display.c

7180

vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);

sys/dev/drm/i915/intel_display.c

7183

dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));

sys/dev/drm/i915/intel_display.c

7188

vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);

sys/dev/drm/i915/intel_display.c

7191

dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));

sys/dev/drm/i915/intel_display.c

7197

vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);

sys/dev/drm/i915/intel_display.c

7222

vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);

sys/dev/drm/i915/intel_display.c

7224

dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));

sys/dev/drm/i915/intel_display.c

7227

vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);

sys/dev/drm/i915/intel_display.c

7230

vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),

sys/dev/drm/i915/intel_display.c

7231

vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |

sys/dev/drm/i915/intel_display.c

7247

int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum i915_pipe pipe,

sys/dev/drm/i915/intel_display.c

7250

struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

7284

void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum i915_pipe pipe)

sys/dev/drm/i915/intel_display.c

7287

chv_disable_pll(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

7289

vlv_disable_pll(dev_priv, pipe);

sys/dev/drm/i915/intel_display.c

7406

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

7459

(pipe == PIPE_B || pipe == PIPE_C))

sys/dev/drm/i915/intel_display.c

7460

I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));

sys/dev/drm/i915/intel_display.c

7468

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

7473

I915_WRITE(PIPESRC(pipe),

sys/dev/drm/i915/intel_display.c

7520

tmp = I915_READ(PIPESRC(crtc->pipe));

sys/dev/drm/i915/intel_display.c

7560

pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;

sys/dev/drm/i915/intel_display.c

7602

I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);

sys/dev/drm/i915/intel_display.c

7603

POSTING_READ(PIPECONF(intel_crtc->pipe));

sys/dev/drm/i915/intel_display.c

7811

if (crtc->pipe != PIPE_B)

sys/dev/drm/i915/intel_display.c

7814

if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))

sys/dev/drm/i915/intel_display.c

7827

int pipe = pipe_config->cpu_transcoder;

sys/dev/drm/i915/intel_display.c

7837

mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));

sys/dev/drm/i915/intel_display.c

7857

enum i915_pipe pipe;

sys/dev/drm/i915/intel_display.c

7864

if (!plane->get_hw_state(plane, &pipe))

sys/dev/drm/i915/intel_display.c

7867

WARN_ON(pipe != crtc->pipe);

sys/dev/drm/i915/intel_display.c

7891

if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&

sys/dev/drm/i915/intel_display.c

7913

val = I915_READ(PIPESRC(pipe));

sys/dev/drm/i915/intel_display.c

7937

int pipe = pipe_config->cpu_transcoder;

sys/dev/drm/i915/intel_display.c

7938

enum dpio_channel port = vlv_pipe_to_channel(pipe);

sys/dev/drm/i915/intel_display.c

7948

cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));

sys/dev/drm/i915/intel_display.c

7949

pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));

sys/dev/drm/i915/intel_display.c

7950

pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));

sys/dev/drm/i915/intel_display.c

7951

pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));

sys/dev/drm/i915/intel_display.c

7952

pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));

sys/dev/drm/i915/intel_display.c

7974

power_domain = POWER_DOMAIN_PIPE(crtc->pipe);

sys/dev/drm/i915/intel_display.c

7978

pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;

sys/dev/drm/i915/intel_display.c

7983

tmp = I915_READ(PIPECONF(crtc->pipe));

sys/dev/drm/i915/intel_display.c

8018

if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)

sys/dev/drm/i915/intel_display.c

8019

tmp = dev_priv->chv_dpll_md[crtc->pipe];

sys/dev/drm/i915/intel_display.c

8021

tmp = I915_READ(DPLL_MD(crtc->pipe));

sys/dev/drm/i915/intel_display.c

8028

tmp = I915_READ(DPLL(crtc->pipe));

sys/dev/drm/i915/intel_display.c

8038

pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));

sys/dev/drm/i915/intel_display.c

8048

pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));

sys/dev/drm/i915/intel_display.c

8049

pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));

sys/dev/drm/i915/intel_display.c

8513

int pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_display.c

8547

I915_WRITE(PIPECONF(pipe), val);

sys/dev/drm/i915/intel_display.c

8548

POSTING_READ(PIPECONF(pipe));

sys/dev/drm/i915/intel_display.c

8606

I915_WRITE(PIPEMISC(intel_crtc->pipe), val);

sys/dev/drm/i915/intel_display.c

8776

pipe_name(crtc->pipe));

sys/dev/drm/i915/intel_display.c

8788

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

8790

m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));

sys/dev/drm/i915/intel_display.c

8791

m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));

sys/dev/drm/i915/intel_display.c

8792

m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))

sys/dev/drm/i915/intel_display.c

8794

m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));

sys/dev/drm/i915/intel_display.c

8795

m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))

sys/dev/drm/i915/intel_display.c

8805

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_display.c

8830

m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));

sys/dev/drm/i915/intel_display.c

8831

m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));

sys/dev/drm/i915/intel_display.c

8832

m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))

sys/dev/drm/i915/intel_display.c

8834

m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));

sys/dev/drm/i915/intel_display.c

8835

m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))

sys/dev/drm/i915/intel_display.c

8870

ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));

sys/dev/drm/i915/intel_display.c

8874

pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));

sys/dev/drm/i915/intel_display.c

8875

pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));

sys/dev/drm/i915/intel_display.c

8896

enum i915_pipe pipe;

sys/dev/drm/i915/intel_display.c

8903

if (!plane->get_hw_state(plane, &pipe))

sys/dev/drm/i915/intel_display.c

8906

WARN_ON(pipe != crtc->pipe);

sys/dev/drm/i915/intel_display.c

8918

val = I915_READ(PLANE_CTL(pipe, plane_id));

sys/dev/drm/i915/intel_display.c

8926

alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));

sys/dev/drm/i915/intel_display.c

8986

base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;

sys/dev/drm/i915/intel_display.c

8989

offset = I915_READ(PLANE_OFFSET(pipe, plane_id));

sys/dev/drm/i915/intel_display.c

8991

val = I915_READ(PLANE_SIZE(pipe, plane_id));

sys/dev/drm/i915/intel_display.c

8995

val = I915_READ(PLANE_STRIDE(pipe, plane_id));

sys/dev/drm/i915/intel_display.c

9022

tmp = I915_READ(PF_CTL(crtc->pipe));

sys/dev/drm/i915/intel_display.c

9026

pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));

sys/dev/drm/i915/intel_display.c

9027

pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));

sys/dev/drm/i915/intel_display.c

9034

PF_PIPE_SEL_IVB(crtc->pipe));

sys/dev/drm/i915/intel_display.c

9048

power_domain = POWER_DOMAIN_PIPE(crtc->pipe);

sys/dev/drm/i915/intel_display.c

9052

pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;

sys/dev/drm/i915/intel_display.c

9056

tmp = I915_READ(PIPECONF(crtc->pipe));

sys/dev/drm/i915/intel_display.c

9080

if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {

sys/dev/drm/i915/intel_display.c

9086

tmp = I915_READ(FDI_RX_CTL(crtc->pipe));

sys/dev/drm/i915/intel_display.c

9097

pll_id = (enum intel_dpll_id) crtc->pipe;

sys/dev/drm/i915/intel_display.c

9100

if (tmp & TRANS_DPLLB_SEL(crtc->pipe))

sys/dev/drm/i915/intel_display.c

9143

pipe_name(crtc->pipe));

sys/dev/drm/i915/intel_display.c

9368

pipe_name(crtc->pipe));

sys/dev/drm/i915/intel_display.c

9519

pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;

sys/dev/drm/i915/intel_display.c

9544

if (trans_edp_pipe == crtc->pipe)

sys/dev/drm/i915/intel_display.c

9596

if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))

sys/dev/drm/i915/intel_display.c

9662

power_domain = POWER_DOMAIN_PIPE(crtc->pipe);

sys/dev/drm/i915/intel_display.c

9688

I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;

sys/dev/drm/i915/intel_display.c

9691

u32 tmp = I915_READ(PIPEMISC(crtc->pipe));

sys/dev/drm/i915/intel_display.c

9707

power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);

sys/dev/drm/i915/intel_display.c

9987

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_display.c

9999

*pipe = PIPE_A;

sys/dev/drm/i915/intel_display.h

263

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)

sys/dev/drm/i915/intel_display.h

264

#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \

sys/dev/drm/i915/intel_display.h

265

((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)

sys/dev/drm/i915/intel_display.h

323

for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)

sys/dev/drm/i915/intel_dp.c

1066

enum i915_pipe pipe = vlv_power_sequencer_pipe(intel_dp);

sys/dev/drm/i915/intel_dp.c

1070

pp_ctrl_reg = PP_CONTROL(pipe);

sys/dev/drm/i915/intel_dp.c

1071

pp_div_reg = PP_DIVISOR(pipe);

sys/dev/drm/i915/intel_dp.c

123

enum i915_pipe pipe);

sys/dev/drm/i915/intel_dp.c

2184

intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);

sys/dev/drm/i915/intel_dp.c

2190

trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));

sys/dev/drm/i915/intel_dp.c

2195

I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);

sys/dev/drm/i915/intel_dp.c

2210

intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);

sys/dev/drm/i915/intel_dp.c

2212

intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);

sys/dev/drm/i915/intel_dp.c

2727

assert_pipe_disabled(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_dp.c

2752

intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);

sys/dev/drm/i915/intel_dp.c

2767

assert_pipe_disabled(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_dp.c

2835

enum port port, enum i915_pipe *pipe)

sys/dev/drm/i915/intel_dp.c

2843

*pipe = p;

sys/dev/drm/i915/intel_dp.c

2851

*pipe = PIPE_A;

sys/dev/drm/i915/intel_dp.c

2858

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_dp.c

2869

*pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;

sys/dev/drm/i915/intel_dp.c

2871

ret &= cpt_dp_port_selected(dev_priv, port, pipe);

sys/dev/drm/i915/intel_dp.c

2873

*pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;

sys/dev/drm/i915/intel_dp.c

2875

*pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;

sys/dev/drm/i915/intel_dp.c

2881

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_dp.c

2892

encoder->port, pipe);

sys/dev/drm/i915/intel_dp.c

2918

u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));

sys/dev/drm/i915/intel_dp.c

3175

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_dp.c

3209

pipe_name(pipe));

sys/dev/drm/i915/intel_dp.c

3247

enum i915_pipe pipe = intel_dp->pps_pipe;

sys/dev/drm/i915/intel_dp.c

3248

i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);

sys/dev/drm/i915/intel_dp.c

3252

if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))

sys/dev/drm/i915/intel_dp.c

3267

pipe_name(pipe), port_name(intel_dig_port->base.port));

sys/dev/drm/i915/intel_dp.c

3275

enum i915_pipe pipe)

sys/dev/drm/i915/intel_dp.c

3285

WARN(intel_dp->active_pipe == pipe,

sys/dev/drm/i915/intel_dp.c

3287

pipe_name(pipe), port_name(port));

sys/dev/drm/i915/intel_dp.c

3289

if (intel_dp->pps_pipe != pipe)

sys/dev/drm/i915/intel_dp.c

3293

pipe_name(pipe), port_name(port));

sys/dev/drm/i915/intel_dp.c

3312

intel_dp->pps_pipe != crtc->pipe) {

sys/dev/drm/i915/intel_dp.c

3325

vlv_steal_power_sequencer(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_dp.c

3327

intel_dp->active_pipe = crtc->pipe;

sys/dev/drm/i915/intel_dp.c

3333

intel_dp->pps_pipe = crtc->pipe;

sys/dev/drm/i915/intel_dp.c

3860

if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {

sys/dev/drm/i915/intel_dp.c

4409

intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);

sys/dev/drm/i915/intel_dp.c

4418

intel_wait_for_vblank(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_dp.c

4420

intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);

sys/dev/drm/i915/intel_dp.c

5594

enum i915_pipe pipe;

sys/dev/drm/i915/intel_dp.c

5597

encoder->port, &pipe))

sys/dev/drm/i915/intel_dp.c

5598

return pipe;

sys/dev/drm/i915/intel_dp.c

6251

enum i915_pipe pipe;

sys/dev/drm/i915/intel_dp.c

6265

pipe = to_intel_crtc(crtc)->pipe;

sys/dev/drm/i915/intel_dp.c

6267

frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);

sys/dev/drm/i915/intel_dp.c

6294

enum i915_pipe pipe;

sys/dev/drm/i915/intel_dp.c

6308

pipe = to_intel_crtc(crtc)->pipe;

sys/dev/drm/i915/intel_dp.c

6310

frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);

sys/dev/drm/i915/intel_dp.c

6424

enum i915_pipe pipe = INVALID_PIPE;

sys/dev/drm/i915/intel_dp.c

6505

pipe = vlv_active_pipe(intel_dp);

sys/dev/drm/i915/intel_dp.c

6507

if (pipe != PIPE_A && pipe != PIPE_B)

sys/dev/drm/i915/intel_dp.c

6508

pipe = intel_dp->pps_pipe;

sys/dev/drm/i915/intel_dp.c

6510

if (pipe != PIPE_A && pipe != PIPE_B)

sys/dev/drm/i915/intel_dp.c

6511

pipe = PIPE_A;

sys/dev/drm/i915/intel_dp.c

6514

pipe_name(pipe));

sys/dev/drm/i915/intel_dp.c

6519

intel_panel_setup_backlight(connector, pipe);

sys/dev/drm/i915/intel_dp.c

713

enum i915_pipe pipe = intel_dp->pps_pipe;

sys/dev/drm/i915/intel_dp.c

715

enum dpio_phy phy = DPIO_PHY(pipe);

sys/dev/drm/i915/intel_dp.c

716

enum dpio_channel ch = vlv_pipe_to_channel(pipe);

sys/dev/drm/i915/intel_dp.c

721

pipe_name(pipe), port_name(intel_dig_port->base.port)))

sys/dev/drm/i915/intel_dp.c

725

pipe_name(pipe), port_name(intel_dig_port->base.port));

sys/dev/drm/i915/intel_dp.c

736

DP |= DP_PIPE_SEL_CHV(pipe);

sys/dev/drm/i915/intel_dp.c

738

DP |= DP_PIPE_SEL(pipe);

sys/dev/drm/i915/intel_dp.c

740

pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;

sys/dev/drm/i915/intel_dp.c

750

if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?

sys/dev/drm/i915/intel_dp.c

753

pipe_name(pipe));

sys/dev/drm/i915/intel_dp.c

774

vlv_force_pll_off(dev_priv, pipe);

sys/dev/drm/i915/intel_dp.c

818

enum i915_pipe pipe;

sys/dev/drm/i915/intel_dp.c

831

pipe = vlv_find_free_pps(dev_priv);

sys/dev/drm/i915/intel_dp.c

837

if (WARN_ON(pipe == INVALID_PIPE))

sys/dev/drm/i915/intel_dp.c

838

pipe = PIPE_A;

sys/dev/drm/i915/intel_dp.c

840

vlv_steal_power_sequencer(dev_priv, pipe);

sys/dev/drm/i915/intel_dp.c

841

intel_dp->pps_pipe = pipe;

sys/dev/drm/i915/intel_dp.c

886

enum i915_pipe pipe);

sys/dev/drm/i915/intel_dp.c

889

enum i915_pipe pipe)

sys/dev/drm/i915/intel_dp.c

891

return I915_READ(PP_STATUS(pipe)) & PP_ON;

sys/dev/drm/i915/intel_dp.c

895

enum i915_pipe pipe)

sys/dev/drm/i915/intel_dp.c

897

return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;

sys/dev/drm/i915/intel_dp.c

901

enum i915_pipe pipe)

sys/dev/drm/i915/intel_dp.c

911

enum i915_pipe pipe;

sys/dev/drm/i915/intel_dp.c

913

for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {

sys/dev/drm/i915/intel_dp.c

914

u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &

sys/dev/drm/i915/intel_dp.c

920

if (!pipe_check(dev_priv, pipe))

sys/dev/drm/i915/intel_dp.c

923

return pipe;

sys/dev/drm/i915/intel_dp_aux_backlight.c

228

enum i915_pipe pipe)

sys/dev/drm/i915/intel_dp_mst.c

291

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_dp_mst.c

294

*pipe = intel_mst->pipe;

sys/dev/drm/i915/intel_dp_mst.c

407

return &intel_dp->mst_encoders[crtc->pipe]->base.base;

sys/dev/drm/i915/intel_dp_mst.c

432

enum i915_pipe pipe;

sys/dev/drm/i915/intel_dp_mst.c

433

if (!connector->encoder->get_hw_state(connector->encoder, &pipe))

sys/dev/drm/i915/intel_dp_mst.c

448

enum i915_pipe pipe;

sys/dev/drm/i915/intel_dp_mst.c

469

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_dp_mst.c

471

&intel_dp->mst_encoders[pipe]->base.base;

sys/dev/drm/i915/intel_dp_mst.c

535

intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum i915_pipe pipe)

sys/dev/drm/i915/intel_dp_mst.c

546

intel_mst->pipe = pipe;

sys/dev/drm/i915/intel_dp_mst.c

551

DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));

sys/dev/drm/i915/intel_dp_mst.c

577

enum i915_pipe pipe;

sys/dev/drm/i915/intel_dp_mst.c

579

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/intel_dp_mst.c

580

intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(intel_dig_port, pipe);

sys/dev/drm/i915/intel_dpio_phy.c

1002

vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);

sys/dev/drm/i915/intel_dpio_phy.c

1004

vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);

sys/dev/drm/i915/intel_dpio_phy.c

1005

vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);

sys/dev/drm/i915/intel_dpio_phy.c

1006

vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);

sys/dev/drm/i915/intel_dpio_phy.c

1017

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_dpio_phy.c

1021

vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),

sys/dev/drm/i915/intel_dpio_phy.c

1024

vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),

sys/dev/drm/i915/intel_dpio_phy.c

1031

vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);

sys/dev/drm/i915/intel_dpio_phy.c

1032

vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);

sys/dev/drm/i915/intel_dpio_phy.c

1033

vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);

sys/dev/drm/i915/intel_dpio_phy.c

1045

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_dpio_phy.c

1051

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));

sys/dev/drm/i915/intel_dpio_phy.c

1053

if (pipe)

sys/dev/drm/i915/intel_dpio_phy.c

1058

vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);

sys/dev/drm/i915/intel_dpio_phy.c

1061

vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);

sys/dev/drm/i915/intel_dpio_phy.c

1062

vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);

sys/dev/drm/i915/intel_dpio_phy.c

1074

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_dpio_phy.c

1077

vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);

sys/dev/drm/i915/intel_dpio_phy.c

1078

vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);

sys/dev/drm/i915/intel_dpio_phy.c

645

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_dpio_phy.c

652

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));

sys/dev/drm/i915/intel_dpio_phy.c

656

vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

659

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));

sys/dev/drm/i915/intel_dpio_phy.c

663

vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

666

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));

sys/dev/drm/i915/intel_dpio_phy.c

669

vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

672

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));

sys/dev/drm/i915/intel_dpio_phy.c

675

vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

680

val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));

sys/dev/drm/i915/intel_dpio_phy.c

683

vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);

sys/dev/drm/i915/intel_dpio_phy.c

688

val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));

sys/dev/drm/i915/intel_dpio_phy.c

701

vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);

sys/dev/drm/i915/intel_dpio_phy.c

711

val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));

sys/dev/drm/i915/intel_dpio_phy.c

716

vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);

sys/dev/drm/i915/intel_dpio_phy.c

720

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));

sys/dev/drm/i915/intel_dpio_phy.c

722

vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

725

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));

sys/dev/drm/i915/intel_dpio_phy.c

727

vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

741

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_dpio_phy.c

744

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));

sys/dev/drm/i915/intel_dpio_phy.c

749

vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

752

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));

sys/dev/drm/i915/intel_dpio_phy.c

757

vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

760

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));

sys/dev/drm/i915/intel_dpio_phy.c

766

vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

769

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));

sys/dev/drm/i915/intel_dpio_phy.c

775

vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

786

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_dpio_phy.c

795

if (ch == DPIO_CH0 && pipe == PIPE_B)

sys/dev/drm/i915/intel_dpio_phy.c

807

if (pipe != PIPE_B) {

sys/dev/drm/i915/intel_dpio_phy.c

808

val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);

sys/dev/drm/i915/intel_dpio_phy.c

814

vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);

sys/dev/drm/i915/intel_dpio_phy.c

816

val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);

sys/dev/drm/i915/intel_dpio_phy.c

822

vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

sys/dev/drm/i915/intel_dpio_phy.c

826

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));

sys/dev/drm/i915/intel_dpio_phy.c

828

if (pipe != PIPE_B)

sys/dev/drm/i915/intel_dpio_phy.c

832

vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

835

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));

sys/dev/drm/i915/intel_dpio_phy.c

837

if (pipe != PIPE_B)

sys/dev/drm/i915/intel_dpio_phy.c

841

vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

849

val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));

sys/dev/drm/i915/intel_dpio_phy.c

850

if (pipe != PIPE_B)

sys/dev/drm/i915/intel_dpio_phy.c

854

vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

867

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_dpio_phy.c

874

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));

sys/dev/drm/i915/intel_dpio_phy.c

876

vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

879

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));

sys/dev/drm/i915/intel_dpio_phy.c

881

vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

891

vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),

sys/dev/drm/i915/intel_dpio_phy.c

907

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));

sys/dev/drm/i915/intel_dpio_phy.c

909

vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

912

val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));

sys/dev/drm/i915/intel_dpio_phy.c

914

vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);

sys/dev/drm/i915/intel_dpio_phy.c

917

vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),

sys/dev/drm/i915/intel_dpio_phy.c

925

vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),

sys/dev/drm/i915/intel_dpio_phy.c

954

enum i915_pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;

sys/dev/drm/i915/intel_dpio_phy.c

960

if (pipe != PIPE_B) {

sys/dev/drm/i915/intel_dpio_phy.c

961

val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);

sys/dev/drm/i915/intel_dpio_phy.c

963

vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);

sys/dev/drm/i915/intel_dpio_phy.c

965

val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);

sys/dev/drm/i915/intel_dpio_phy.c

967

vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);

sys/dev/drm/i915/intel_dpio_phy.c

992

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_dpio_phy.c

995

vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);

sys/dev/drm/i915/intel_dpio_phy.c

996

vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);

sys/dev/drm/i915/intel_dpio_phy.c

997

vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),

sys/dev/drm/i915/intel_dpio_phy.c

999

vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);

sys/dev/drm/i915/intel_dpll_mgr.c

1696

clock, pipe_name(intel_crtc->pipe));

sys/dev/drm/i915/intel_dpll_mgr.c

304

pipe_name(crtc->pipe));

sys/dev/drm/i915/intel_dpll_mgr.c

306

shared_dpll[id].crtc_mask |= 1 << crtc->pipe;

sys/dev/drm/i915/intel_dpll_mgr.c

3318

shared_dpll_state[dpll->info->id].crtc_mask &= ~(1 << crtc->pipe);

sys/dev/drm/i915/intel_dpll_mgr.c

418

assert_pch_transcoder_disabled(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_dpll_mgr.c

436

i = (enum intel_dpll_id) crtc->pipe;

sys/dev/drm/i915/intel_drv.h

1203

enum i915_pipe pipe;

sys/dev/drm/i915/intel_drv.h

1237

vlv_pipe_to_channel(enum i915_pipe pipe)

sys/dev/drm/i915/intel_drv.h

1239

switch (pipe) {

sys/dev/drm/i915/intel_drv.h

1251

intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe)

sys/dev/drm/i915/intel_drv.h

1253

return dev_priv->pipe_to_crtc_mapping[pipe];

sys/dev/drm/i915/intel_drv.h

1372

enum i915_pipe pipe, bool enable);

sys/dev/drm/i915/intel_drv.h

1377

enum i915_pipe pipe);

sys/dev/drm/i915/intel_drv.h

1421

i915_reg_t adpa_reg, enum i915_pipe *pipe);

sys/dev/drm/i915/intel_drv.h

1432

bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum i915_pipe *pipe);

sys/dev/drm/i915/intel_drv.h

1501

void i830_enable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe);

sys/dev/drm/i915/intel_drv.h

1502

void i830_disable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe);

sys/dev/drm/i915/intel_drv.h

1544

enum i915_pipe pipe);

sys/dev/drm/i915/intel_drv.h

1560

intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum i915_pipe pipe)

sys/dev/drm/i915/intel_drv.h

1562

drm_wait_one_vblank(&dev_priv->drm, pipe);

sys/dev/drm/i915/intel_drv.h

1565

intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)

sys/dev/drm/i915/intel_drv.h

1567

const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_drv.h

1570

intel_wait_for_vblank(dev_priv, pipe);

sys/dev/drm/i915/intel_drv.h

1613

enum i915_pipe pipe);

sys/dev/drm/i915/intel_drv.h

1615

int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum i915_pipe pipe,

sys/dev/drm/i915/intel_drv.h

1617

void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum i915_pipe pipe);

sys/dev/drm/i915/intel_drv.h

1622

enum i915_pipe pipe);

sys/dev/drm/i915/intel_drv.h

1624

enum i915_pipe pipe, bool state);

sys/dev/drm/i915/intel_drv.h

1631

enum i915_pipe pipe, bool state);

sys/dev/drm/i915/intel_drv.h

1634

void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, bool state);

sys/dev/drm/i915/intel_drv.h

1698

enum i915_pipe *pipe);

sys/dev/drm/i915/intel_drv.h

1879

i915_reg_t lvds_reg, enum i915_pipe *pipe);

sys/dev/drm/i915/intel_drv.h

1921

enum i915_pipe pipe);

sys/dev/drm/i915/intel_drv.h

2131

i915_reg_t sdvo_reg, enum i915_pipe *pipe);

sys/dev/drm/i915/intel_drv.h

2140

enum i915_pipe pipe, int plane);

sys/dev/drm/i915/intel_drv.h

2149

bool skl_plane_get_hw_state(struct intel_plane *plane, enum i915_pipe *pipe);

sys/dev/drm/i915/intel_drv.h

2151

enum i915_pipe pipe, enum plane_id plane_id);

sys/dev/drm/i915/intel_drv.h

2153

enum i915_pipe pipe, enum plane_id plane_id);

sys/dev/drm/i915/intel_drv.h

261

bool (*get_hw_state)(struct intel_encoder *, enum i915_pipe *pipe);

sys/dev/drm/i915/intel_drv.h

308

int (*setup)(struct intel_connector *connector, enum i915_pipe pipe);

sys/dev/drm/i915/intel_drv.h

921

enum i915_pipe pipe;

sys/dev/drm/i915/intel_drv.h

968

enum i915_pipe pipe;

sys/dev/drm/i915/intel_drv.h

991

bool (*get_hw_state)(struct intel_plane *plane, enum i915_pipe *pipe);

sys/dev/drm/i915/intel_dvo.c

138

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_dvo.c

146

*pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;

sys/dev/drm/i915/intel_dvo.c

270

int pipe = crtc->pipe;

sys/dev/drm/i915/intel_dvo.c

281

dvo_val |= DVO_PIPE_SEL(pipe);

sys/dev/drm/i915/intel_dvo.c

440

enum i915_pipe pipe;

sys/dev/drm/i915/intel_dvo.c

477

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_dvo.c

478

dpll[pipe] = I915_READ(DPLL(pipe));

sys/dev/drm/i915/intel_dvo.c

479

I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);

sys/dev/drm/i915/intel_dvo.c

485

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_dvo.c

486

I915_WRITE(DPLL(pipe), dpll[pipe]);

sys/dev/drm/i915/intel_fbc.c

1102

DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));

sys/dev/drm/i915/intel_fbc.c

1254

dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);

sys/dev/drm/i915/intel_fbc.c

338

I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),

sys/dev/drm/i915/intel_fbc.c

339

I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |

sys/dev/drm/i915/intel_fbc.c

420

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_fbc.c

427

fbc->visible_pipes_mask |= (1 << pipe);

sys/dev/drm/i915/intel_fbc.c

429

fbc->visible_pipes_mask &= ~(1 << pipe);

sys/dev/drm/i915/intel_fbc.c

431

return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;

sys/dev/drm/i915/intel_fbc.c

829

params->crtc.pipe = crtc->pipe;

sys/dev/drm/i915/intel_fbc.c

889

DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));

sys/dev/drm/i915/intel_fbdev.c

584

pipe_name(intel_crtc->pipe));

sys/dev/drm/i915/intel_fbdev.c

590

pipe_name(intel_crtc->pipe));

sys/dev/drm/i915/intel_fbdev.c

609

pipe_name(intel_crtc->pipe));

sys/dev/drm/i915/intel_fbdev.c

614

pipe_name(intel_crtc->pipe));

sys/dev/drm/i915/intel_fbdev.c

625

pipe_name(intel_crtc->pipe),

sys/dev/drm/i915/intel_fbdev.c

635

pipe_name(intel_crtc->pipe),

sys/dev/drm/i915/intel_fbdev.c

643

pipe_name(intel_crtc->pipe),

sys/dev/drm/i915/intel_fbdev.c

650

pipe_name(intel_crtc->pipe),

sys/dev/drm/i915/intel_fifo_underrun.c

102

trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

103

DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));

sys/dev/drm/i915/intel_fifo_underrun.c

107

enum i915_pipe pipe,

sys/dev/drm/i915/intel_fifo_underrun.c

111

i915_reg_t reg = PIPESTAT(pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

116

u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

122

DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));

sys/dev/drm/i915/intel_fifo_underrun.c

127

enum i915_pipe pipe, bool enable)

sys/dev/drm/i915/intel_fifo_underrun.c

130

uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :

sys/dev/drm/i915/intel_fifo_underrun.c

142

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_fifo_underrun.c

147

if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)

sys/dev/drm/i915/intel_fifo_underrun.c

150

I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

sys/dev/drm/i915/intel_fifo_underrun.c

153

trace_intel_cpu_fifo_underrun(dev_priv, pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

154

DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe));

sys/dev/drm/i915/intel_fifo_underrun.c

158

enum i915_pipe pipe,

sys/dev/drm/i915/intel_fifo_underrun.c

163

I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

sys/dev/drm/i915/intel_fifo_underrun.c

173

I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {

sys/dev/drm/i915/intel_fifo_underrun.c

175

pipe_name(pipe));

sys/dev/drm/i915/intel_fifo_underrun.c

181

enum i915_pipe pipe, bool enable)

sys/dev/drm/i915/intel_fifo_underrun.c

186

bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);

sys/dev/drm/i915/intel_fifo_underrun.c

188

bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);

sys/dev/drm/i915/intel_fifo_underrun.c

208

enum i915_pipe pch_transcoder = crtc->pipe;

sys/dev/drm/i915/intel_fifo_underrun.c

250

enum i915_pipe pipe, bool enable)

sys/dev/drm/i915/intel_fifo_underrun.c

253

struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

262

i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);

sys/dev/drm/i915/intel_fifo_underrun.c

264

ironlake_set_fifo_underrun_reporting(dev, pipe, enable);

sys/dev/drm/i915/intel_fifo_underrun.c

266

ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);

sys/dev/drm/i915/intel_fifo_underrun.c

268

broadwell_set_fifo_underrun_reporting(dev, pipe, enable);

sys/dev/drm/i915/intel_fifo_underrun.c

290

enum i915_pipe pipe, bool enable)

sys/dev/drm/i915/intel_fifo_underrun.c

296

ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,

sys/dev/drm/i915/intel_fifo_underrun.c

363

enum i915_pipe pipe)

sys/dev/drm/i915/intel_fifo_underrun.c

365

struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

376

if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {

sys/dev/drm/i915/intel_fifo_underrun.c

377

trace_intel_cpu_fifo_underrun(dev_priv, pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

379

pipe_name(pipe));

sys/dev/drm/i915/intel_fifo_underrun.c

55

enum i915_pipe pipe;

sys/dev/drm/i915/intel_fifo_underrun.c

59

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_fifo_underrun.c

60

crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

72

enum i915_pipe pipe;

sys/dev/drm/i915/intel_fifo_underrun.c

77

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_fifo_underrun.c

78

crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

90

i915_reg_t reg = PIPESTAT(crtc->pipe);

sys/dev/drm/i915/intel_fifo_underrun.c

98

enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

1165

hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

1167

hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

1169

hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

1176

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_hdmi.c

1186

ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);

sys/dev/drm/i915/intel_hdmi.c

1253

pipe_name(crtc->pipe));

sys/dev/drm/i915/intel_hdmi.c

1337

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_hdmi.c

1357

I915_WRITE(TRANS_CHICKEN1(pipe),

sys/dev/drm/i915/intel_hdmi.c

1358

I915_READ(TRANS_CHICKEN1(pipe)) |

sys/dev/drm/i915/intel_hdmi.c

1375

I915_WRITE(TRANS_CHICKEN1(pipe),

sys/dev/drm/i915/intel_hdmi.c

1376

I915_READ(TRANS_CHICKEN1(pipe)) &

sys/dev/drm/i915/intel_hdmi.c

1413

if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {

sys/dev/drm/i915/intel_hdmi.c

215

i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

230

I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);

sys/dev/drm/i915/intel_hdmi.c

235

I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);

sys/dev/drm/i915/intel_hdmi.c

251

enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;

sys/dev/drm/i915/intel_hdmi.c

252

i915_reg_t reg = TVIDEO_DIP_CTL(pipe);

sys/dev/drm/i915/intel_hdmi.c

275

i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

293

I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);

sys/dev/drm/i915/intel_hdmi.c

298

I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);

sys/dev/drm/i915/intel_hdmi.c

313

enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;

sys/dev/drm/i915/intel_hdmi.c

314

u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));

sys/dev/drm/i915/intel_hdmi.c

333

i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

348

I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);

sys/dev/drm/i915/intel_hdmi.c

353

I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);

sys/dev/drm/i915/intel_hdmi.c

369

enum i915_pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;

sys/dev/drm/i915/intel_hdmi.c

370

u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));

sys/dev/drm/i915/intel_hdmi.c

672

reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

674

reg = TVIDEO_DIP_GCP(crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

701

i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

753

i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_hdmi.c

797

i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);

sys/dev/drm/i915/intel_lpe_audio.c

117

pdata->port[0].pipe = -1;

sys/dev/drm/i915/intel_lpe_audio.c

118

pdata->port[1].pipe = -1;

sys/dev/drm/i915/intel_lpe_audio.c

119

pdata->port[2].pipe = -1;

sys/dev/drm/i915/intel_lpe_audio.c

326

enum i915_pipe pipe, enum port port,

sys/dev/drm/i915/intel_lpe_audio.c

347

ppdata->pipe = pipe;

sys/dev/drm/i915/intel_lpe_audio.c

356

ppdata->pipe = -1;

sys/dev/drm/i915/intel_lvds.c

104

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_lvds.c

114

ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);

sys/dev/drm/i915/intel_lvds.c

241

int pipe = crtc->pipe;

sys/dev/drm/i915/intel_lvds.c

245

assert_fdi_rx_pll_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_lvds.c

249

assert_pll_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_lvds.c

259

temp |= LVDS_PIPE_SEL_CPT(pipe);

sys/dev/drm/i915/intel_lvds.c

262

temp |= LVDS_PIPE_SEL(pipe);

sys/dev/drm/i915/intel_lvds.c

406

if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {

sys/dev/drm/i915/intel_lvds.c

88

i915_reg_t lvds_reg, enum i915_pipe *pipe)

sys/dev/drm/i915/intel_lvds.c

96

*pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;

sys/dev/drm/i915/intel_lvds.c

98

*pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;

sys/dev/drm/i915/intel_overlay.c

281

enum i915_pipe pipe = overlay->crtc->pipe;

sys/dev/drm/i915/intel_overlay.c

287

INTEL_FRONTBUFFER_OVERLAY(pipe));

sys/dev/drm/i915/intel_overlay.c

290

INTEL_FRONTBUFFER_OVERLAY(pipe));

sys/dev/drm/i915/intel_overlay.c

349

INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));

sys/dev/drm/i915/intel_overlay.c

753

enum i915_pipe pipe = overlay->crtc->pipe;

sys/dev/drm/i915/intel_overlay.c

785

oconfig |= pipe == 0 ?

sys/dev/drm/i915/intel_panel.c

1007

enum i915_pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;

sys/dev/drm/i915/intel_panel.c

1022

I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) |

sys/dev/drm/i915/intel_panel.c

1096

enum i915_pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;

sys/dev/drm/i915/intel_panel.c

1101

DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));

sys/dev/drm/i915/intel_panel.c

1634

static int vlv_setup_backlight(struct intel_connector *connector, enum i915_pipe pipe)

sys/dev/drm/i915/intel_panel.c

1640

if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))

sys/dev/drm/i915/intel_panel.c

1643

ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));

sys/dev/drm/i915/intel_panel.c

1646

ctl = I915_READ(VLV_BLC_PWM_CTL(pipe));

sys/dev/drm/i915/intel_panel.c

1657

val = _vlv_get_backlight(dev_priv, pipe);

sys/dev/drm/i915/intel_panel.c

1746

enum i915_pipe pipe)

sys/dev/drm/i915/intel_panel.c

1844

int intel_panel_setup_backlight(struct drm_connector *connector, enum i915_pipe pipe)

sys/dev/drm/i915/intel_panel.c

1866

ret = panel->backlight.setup(intel_connector, pipe);

sys/dev/drm/i915/intel_panel.c

360

pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |

sys/dev/drm/i915/intel_panel.c

497

static u32 _vlv_get_backlight(struct drm_i915_private *dev_priv, enum i915_pipe pipe)

sys/dev/drm/i915/intel_panel.c

499

if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))

sys/dev/drm/i915/intel_panel.c

502

return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/drm/i915/intel_panel.c

508

enum i915_pipe pipe = intel_get_pipe_from_connector(connector);

sys/dev/drm/i915/intel_panel.c

510

return _vlv_get_backlight(dev_priv, pipe);

sys/dev/drm/i915/intel_panel.c

581

enum i915_pipe pipe = to_intel_crtc(conn_state->crtc)->pipe;

sys/dev/drm/i915/intel_panel.c

584

tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;

sys/dev/drm/i915/intel_panel.c

585

I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level);

sys/dev/drm/i915/intel_panel.c

717

enum i915_pipe pipe = to_intel_crtc(old_conn_state->crtc)->pipe;

sys/dev/drm/i915/intel_panel.c

722

tmp = I915_READ(VLV_BLC_PWM_CTL2(pipe));

sys/dev/drm/i915/intel_panel.c

723

I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp & ~BLM_PWM_ENABLE);

sys/dev/drm/i915/intel_panel.c

942

enum i915_pipe pipe = to_intel_crtc(conn_state->crtc)->pipe;

sys/dev/drm/i915/intel_panel.c

959

ctl2 = BLM_PIPE(pipe);

sys/dev/drm/i915/intel_panel.c

977

enum i915_pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;

sys/dev/drm/i915/intel_panel.c

980

ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));

sys/dev/drm/i915/intel_panel.c

984

I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2);

sys/dev/drm/i915/intel_panel.c

988

I915_WRITE(VLV_BLC_PWM_CTL(pipe), ctl);

sys/dev/drm/i915/intel_panel.c

996

I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2);

sys/dev/drm/i915/intel_panel.c

997

POSTING_READ(VLV_BLC_PWM_CTL2(pipe));

sys/dev/drm/i915/intel_panel.c

998

I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE);

sys/dev/drm/i915/intel_pm.c

1000

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |

sys/dev/drm/i915/intel_pm.c

1001

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));

sys/dev/drm/i915/intel_pm.c

1003

FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |

sys/dev/drm/i915/intel_pm.c

1004

FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));

sys/dev/drm/i915/intel_pm.c

1006

FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |

sys/dev/drm/i915/intel_pm.c

1007

FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));

sys/dev/drm/i915/intel_pm.c

1010

FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |

sys/dev/drm/i915/intel_pm.c

1011

FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |

sys/dev/drm/i915/intel_pm.c

1012

FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |

sys/dev/drm/i915/intel_pm.c

1013

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |

sys/dev/drm/i915/intel_pm.c

1014

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |

sys/dev/drm/i915/intel_pm.c

1015

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |

sys/dev/drm/i915/intel_pm.c

1016

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |

sys/dev/drm/i915/intel_pm.c

1017

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |

sys/dev/drm/i915/intel_pm.c

1018

FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));

sys/dev/drm/i915/intel_pm.c

1021

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |

sys/dev/drm/i915/intel_pm.c

1022

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));

sys/dev/drm/i915/intel_pm.c

1025

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |

sys/dev/drm/i915/intel_pm.c

1026

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |

sys/dev/drm/i915/intel_pm.c

1027

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |

sys/dev/drm/i915/intel_pm.c

1028

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |

sys/dev/drm/i915/intel_pm.c

1029

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |

sys/dev/drm/i915/intel_pm.c

1030

FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));

sys/dev/drm/i915/intel_pm.c

1511

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_pm.c

1513

wm->pipe[pipe] = wm_state->wm;

sys/dev/drm/i915/intel_pm.c

1896

wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;

sys/dev/drm/i915/intel_pm.c

1969

switch (crtc->pipe) {

sys/dev/drm/i915/intel_pm.c

2115

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_pm.c

2117

wm->pipe[pipe] = wm_state->wm[wm->level];

sys/dev/drm/i915/intel_pm.c

2121

wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;

sys/dev/drm/i915/intel_pm.c

2122

wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;

sys/dev/drm/i915/intel_pm.c

2123

wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;

sys/dev/drm/i915/intel_pm.c

2124

wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;

sys/dev/drm/i915/intel_pm.c

3397

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_pm.c

3404

results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;

sys/dev/drm/i915/intel_pm.c

3406

results->wm_pipe[pipe] =

sys/dev/drm/i915/intel_pm.c

3442

#define WM_DIRTY_PIPE(pipe) (1 << (pipe))

sys/dev/drm/i915/intel_pm.c

3443

#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))

sys/dev/drm/i915/intel_pm.c

3454

enum i915_pipe pipe;

sys/dev/drm/i915/intel_pm.c

3457

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_pm.c

3458

if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {

sys/dev/drm/i915/intel_pm.c

3459

dirty |= WM_DIRTY_LINETIME(pipe);

sys/dev/drm/i915/intel_pm.c

3464

if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {

sys/dev/drm/i915/intel_pm.c

3465

dirty |= WM_DIRTY_PIPE(pipe);

sys/dev/drm/i915/intel_pm.c

3756

enum i915_pipe pipe;

sys/dev/drm/i915/intel_pm.c

3782

pipe = ffs(intel_state->active_crtcs) - 1;

sys/dev/drm/i915/intel_pm.c

3783

crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

sys/dev/drm/i915/intel_pm.c

3867

enum i915_pipe for_pipe = to_intel_crtc(for_crtc)->pipe;

sys/dev/drm/i915/intel_pm.c

3911

enum i915_pipe pipe;

sys/dev/drm/i915/intel_pm.c

3916

pipe = to_intel_crtc(crtc)->pipe;

sys/dev/drm/i915/intel_pm.c

3921

if (pipe < for_pipe)

sys/dev/drm/i915/intel_pm.c

3923

else if (pipe == for_pipe)

sys/dev/drm/i915/intel_pm.c

3957

const enum i915_pipe pipe,

sys/dev/drm/i915/intel_pm.c

3966

val = I915_READ(CUR_BUF_CFG(pipe));

sys/dev/drm/i915/intel_pm.c

3968

&ddb->plane[pipe][plane_id], val);

sys/dev/drm/i915/intel_pm.c

3972

val = I915_READ(PLANE_CTL(pipe, plane_id));

sys/dev/drm/i915/intel_pm.c

3983

val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));

sys/dev/drm/i915/intel_pm.c

3989

val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));

sys/dev/drm/i915/intel_pm.c

3993

&ddb->plane[pipe][plane_id], val2);

sys/dev/drm/i915/intel_pm.c

3995

&ddb->uv_plane[pipe][plane_id], val);

sys/dev/drm/i915/intel_pm.c

3998

&ddb->plane[pipe][plane_id], val);

sys/dev/drm/i915/intel_pm.c

4014

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_pm.c

4016

power_domain = POWER_DOMAIN_PIPE(pipe);

sys/dev/drm/i915/intel_pm.c

4021

skl_ddb_get_hw_plane_state(dev_priv, pipe,

sys/dev/drm/i915/intel_pm.c

4359

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_pm.c

4372

memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));

sys/dev/drm/i915/intel_pm.c

4373

memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));

sys/dev/drm/i915/intel_pm.c

4413

ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];

sys/dev/drm/i915/intel_pm.c

4414

ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;

sys/dev/drm/i915/intel_pm.c

4446

ddb->plane[pipe][plane_id].start = start;

sys/dev/drm/i915/intel_pm.c

4447

ddb->plane[pipe][plane_id].end = start + plane_blocks;

sys/dev/drm/i915/intel_pm.c

4460

ddb->uv_plane[pipe][plane_id].start = start;

sys/dev/drm/i915/intel_pm.c

4461

ddb->uv_plane[pipe][plane_id].end =

sys/dev/drm/i915/intel_pm.c

477

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_pm.c

480

switch (pipe) {

sys/dev/drm/i915/intel_pm.c

4827

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_pm.c

4836

skl_ddb_entry_size(&ddb->uv_plane[pipe][intel_plane_id]) :

sys/dev/drm/i915/intel_pm.c

4837

skl_ddb_entry_size(&ddb->plane[pipe][intel_plane_id]);

sys/dev/drm/i915/intel_pm.c

4969

enum i915_pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe;

sys/dev/drm/i915/intel_pm.c

4973

ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);

sys/dev/drm/i915/intel_pm.c

501

MISSING_CASE(pipe);

sys/dev/drm/i915/intel_pm.c

5046

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_pm.c

5049

skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),

sys/dev/drm/i915/intel_pm.c

5052

skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),

sys/dev/drm/i915/intel_pm.c

5055

skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),

sys/dev/drm/i915/intel_pm.c

5056

&ddb->plane[pipe][plane_id]);

sys/dev/drm/i915/intel_pm.c

5060

PLANE_BUF_CFG(pipe, plane_id),

sys/dev/drm/i915/intel_pm.c

5061

&ddb->plane[pipe][plane_id]);

sys/dev/drm/i915/intel_pm.c

5063

skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),

sys/dev/drm/i915/intel_pm.c

5064

&ddb->uv_plane[pipe][plane_id]);

sys/dev/drm/i915/intel_pm.c

5066

PLANE_NV12_BUF_CFG(pipe, plane_id),

sys/dev/drm/i915/intel_pm.c

5067

&ddb->plane[pipe][plane_id]);

sys/dev/drm/i915/intel_pm.c

5069

skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),

sys/dev/drm/i915/intel_pm.c

5070

&ddb->plane[pipe][plane_id]);

sys/dev/drm/i915/intel_pm.c

5071

I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);

sys/dev/drm/i915/intel_pm.c

5083

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_pm.c

5086

skl_write_wm_level(dev_priv, CUR_WM(pipe, level),

sys/dev/drm/i915/intel_pm.c

5089

skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);

sys/dev/drm/i915/intel_pm.c

5091

skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),

sys/dev/drm/i915/intel_pm.c

5092

&ddb->plane[pipe][PLANE_CURSOR]);

sys/dev/drm/i915/intel_pm.c

5120

enum i915_pipe pipe;

sys/dev/drm/i915/intel_pm.c

5122

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_pm.c

5123

if (pipe != ignore && entries[pipe] &&

sys/dev/drm/i915/intel_pm.c

5124

skl_ddb_entries_overlap(ddb, entries[pipe]))

sys/dev/drm/i915/intel_pm.c

5178

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_pm.c

5183

if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],

sys/dev/drm/i915/intel_pm.c

5184

&new_ddb->plane[pipe][plane_id]) &&

sys/dev/drm/i915/intel_pm.c

5185

skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],

sys/dev/drm/i915/intel_pm.c

5186

&new_ddb->uv_plane[pipe][plane_id]))

sys/dev/drm/i915/intel_pm.c

5238

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_pm.c

5244

old = &old_ddb->plane[pipe][plane_id];

sys/dev/drm/i915/intel_pm.c

5245

new = &new_ddb->plane[pipe][plane_id];

sys/dev/drm/i915/intel_pm.c

5415

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_pm.c

5421

I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);

sys/dev/drm/i915/intel_pm.c

5441

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_pm.c

5451

memcpy(hw_vals->ddb.uv_plane[pipe], results->ddb.uv_plane[pipe],

sys/dev/drm/i915/intel_pm.c

5452

sizeof(hw_vals->ddb.uv_plane[pipe]));

sys/dev/drm/i915/intel_pm.c

5453

memcpy(hw_vals->ddb.plane[pipe], results->ddb.plane[pipe],

sys/dev/drm/i915/intel_pm.c

5454

sizeof(hw_vals->ddb.plane[pipe]));

sys/dev/drm/i915/intel_pm.c

5550

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_pm.c

5562

val = I915_READ(PLANE_WM(pipe, plane_id, level));

sys/dev/drm/i915/intel_pm.c

5564

val = I915_READ(CUR_WM(pipe, level));

sys/dev/drm/i915/intel_pm.c

5570

val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));

sys/dev/drm/i915/intel_pm.c

5572

val = I915_READ(CUR_WM_TRANS(pipe));

sys/dev/drm/i915/intel_pm.c

5580

out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));

sys/dev/drm/i915/intel_pm.c

5624

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/intel_pm.c

5631

hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);

sys/dev/drm/i915/intel_pm.c

5633

hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));

sys/dev/drm/i915/intel_pm.c

5640

u32 tmp = hw->wm_pipe[pipe];

sys/dev/drm/i915/intel_pm.c

5652

active->linetime = hw->wm_linetime[pipe];

sys/dev/drm/i915/intel_pm.c

5680

wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);

sys/dev/drm/i915/intel_pm.c

5681

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);

sys/dev/drm/i915/intel_pm.c

5682

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);

sys/dev/drm/i915/intel_pm.c

5688

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);

sys/dev/drm/i915/intel_pm.c

5689

wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);

sys/dev/drm/i915/intel_pm.c

5690

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);

sys/dev/drm/i915/intel_pm.c

5702

enum i915_pipe pipe;

sys/dev/drm/i915/intel_pm.c

5705

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_pm.c

5706

tmp = I915_READ(VLV_DDL(pipe));

sys/dev/drm/i915/intel_pm.c

5708

wm->ddl[pipe].plane[PLANE_PRIMARY] =

sys/dev/drm/i915/intel_pm.c

5710

wm->ddl[pipe].plane[PLANE_CURSOR] =

sys/dev/drm/i915/intel_pm.c

5712

wm->ddl[pipe].plane[PLANE_SPRITE0] =

sys/dev/drm/i915/intel_pm.c

5714

wm->ddl[pipe].plane[PLANE_SPRITE1] =

sys/dev/drm/i915/intel_pm.c

5720

wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);

sys/dev/drm/i915/intel_pm.c

5721

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);

sys/dev/drm/i915/intel_pm.c

5722

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);

sys/dev/drm/i915/intel_pm.c

5725

wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);

sys/dev/drm/i915/intel_pm.c

5726

wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);

sys/dev/drm/i915/intel_pm.c

5727

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);

sys/dev/drm/i915/intel_pm.c

5734

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);

sys/dev/drm/i915/intel_pm.c

5735

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);

sys/dev/drm/i915/intel_pm.c

5738

wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);

sys/dev/drm/i915/intel_pm.c

5739

wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);

sys/dev/drm/i915/intel_pm.c

5742

wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);

sys/dev/drm/i915/intel_pm.c

5743

wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);

sys/dev/drm/i915/intel_pm.c

5747

wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5748

wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5749

wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5750

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5751

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5752

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5753

wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5754

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5755

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5758

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);

sys/dev/drm/i915/intel_pm.c

5759

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);

sys/dev/drm/i915/intel_pm.c

5763

wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5764

wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5765

wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5766

wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5767

wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5768

wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;

sys/dev/drm/i915/intel_pm.c

5790

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_pm.c

5803

wm->pipe[pipe].plane[plane_id];

sys/dev/drm/i915/intel_pm.c

5846

pipe_name(pipe),

sys/dev/drm/i915/intel_pm.c

5847

wm->pipe[pipe].plane[PLANE_PRIMARY],

sys/dev/drm/i915/intel_pm.c

5848

wm->pipe[pipe].plane[PLANE_CURSOR],

sys/dev/drm/i915/intel_pm.c

5849

wm->pipe[pipe].plane[PLANE_SPRITE0]);

sys/dev/drm/i915/intel_pm.c

5869

intel_get_crtc_for_pipe(dev_priv, plane->pipe);

sys/dev/drm/i915/intel_pm.c

5968

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_pm.c

5986

wm->pipe[pipe].plane[plane_id];

sys/dev/drm/i915/intel_pm.c

6003

pipe_name(pipe),

sys/dev/drm/i915/intel_pm.c

6004

wm->pipe[pipe].plane[PLANE_PRIMARY],

sys/dev/drm/i915/intel_pm.c

6005

wm->pipe[pipe].plane[PLANE_CURSOR],

sys/dev/drm/i915/intel_pm.c

6006

wm->pipe[pipe].plane[PLANE_SPRITE0],

sys/dev/drm/i915/intel_pm.c

6007

wm->pipe[pipe].plane[PLANE_SPRITE1]);

sys/dev/drm/i915/intel_pm.c

6023

intel_get_crtc_for_pipe(dev_priv, plane->pipe);

sys/dev/drm/i915/intel_pm.c

8488

enum i915_pipe pipe;

sys/dev/drm/i915/intel_pm.c

8490

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_pm.c

8491

I915_WRITE(DSPCNTR(pipe),

sys/dev/drm/i915/intel_pm.c

8492

I915_READ(DSPCNTR(pipe)) |

sys/dev/drm/i915/intel_pm.c

8495

I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));

sys/dev/drm/i915/intel_pm.c

8496

POSTING_READ(DSPSURF(pipe));

sys/dev/drm/i915/intel_pm.c

8573

int pipe;

sys/dev/drm/i915/intel_pm.c

8589

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_pm.c

8590

val = I915_READ(TRANS_CHICKEN2(pipe));

sys/dev/drm/i915/intel_pm.c

8598

I915_WRITE(TRANS_CHICKEN2(pipe), val);

sys/dev/drm/i915/intel_pm.c

8601

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_pm.c

8602

I915_WRITE(TRANS_CHICKEN1(pipe),

sys/dev/drm/i915/intel_pm.c

8883

enum i915_pipe pipe;

sys/dev/drm/i915/intel_pm.c

8893

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_pm.c

8894

I915_WRITE(CHICKEN_PIPESL_1(pipe),

sys/dev/drm/i915/intel_pm.c

8895

I915_READ(CHICKEN_PIPESL_1(pipe)) |

sys/dev/drm/i915/intel_pm.c

931

enum i915_pipe pipe;

sys/dev/drm/i915/intel_pm.c

933

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/intel_pm.c

934

trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);

sys/dev/drm/i915/intel_pm.c

938

FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |

sys/dev/drm/i915/intel_pm.c

939

FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |

sys/dev/drm/i915/intel_pm.c

940

FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));

sys/dev/drm/i915/intel_pm.c

945

FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |

sys/dev/drm/i915/intel_pm.c

946

FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |

sys/dev/drm/i915/intel_pm.c

947

FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));

sys/dev/drm/i915/intel_pm.c

963

enum i915_pipe pipe;

sys/dev/drm/i915/intel_pm.c

965

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_pm.c

966

trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);

sys/dev/drm/i915/intel_pm.c

968

I915_WRITE(VLV_DDL(pipe),

sys/dev/drm/i915/intel_pm.c

969

(wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |

sys/dev/drm/i915/intel_pm.c

970

(wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |

sys/dev/drm/i915/intel_pm.c

971

(wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |

sys/dev/drm/i915/intel_pm.c

972

(wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));

sys/dev/drm/i915/intel_pm.c

988

FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |

sys/dev/drm/i915/intel_pm.c

989

FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |

sys/dev/drm/i915/intel_pm.c

990

FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));

sys/dev/drm/i915/intel_pm.c

992

FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |

sys/dev/drm/i915/intel_pm.c

993

FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |

sys/dev/drm/i915/intel_pm.c

994

FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));

sys/dev/drm/i915/intel_psr.c

1007

enum i915_pipe pipe;

sys/dev/drm/i915/intel_psr.c

1022

pipe = to_intel_crtc(crtc)->pipe;

sys/dev/drm/i915/intel_psr.c

1024

frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);

sys/dev/drm/i915/intel_psr.c

1041

I915_WRITE(CURSURFLIVE(pipe), 0);

sys/dev/drm/i915/intel_psr.c

964

enum i915_pipe pipe;

sys/dev/drm/i915/intel_psr.c

979

pipe = to_intel_crtc(crtc)->pipe;

sys/dev/drm/i915/intel_psr.c

981

frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);

sys/dev/drm/i915/intel_runtime_pm.c

1001

if (pipe != PIPE_A)

sys/dev/drm/i915/intel_runtime_pm.c

1004

I915_WRITE(DPLL(pipe), val);

sys/dev/drm/i915/intel_runtime_pm.c

1090

enum i915_pipe pipe;

sys/dev/drm/i915/intel_runtime_pm.c

1092

for_each_pipe(dev_priv, pipe)

sys/dev/drm/i915/intel_runtime_pm.c

1093

assert_pll_disabled(dev_priv, pipe);

sys/dev/drm/i915/intel_runtime_pm.c

1217

enum i915_pipe pipe;

sys/dev/drm/i915/intel_runtime_pm.c

1224

pipe = PIPE_A;

sys/dev/drm/i915/intel_runtime_pm.c

1227

pipe = PIPE_C;

sys/dev/drm/i915/intel_runtime_pm.c

1246

tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);

sys/dev/drm/i915/intel_runtime_pm.c

1249

vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);

sys/dev/drm/i915/intel_runtime_pm.c

1252

tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);

sys/dev/drm/i915/intel_runtime_pm.c

1254

vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);

sys/dev/drm/i915/intel_runtime_pm.c

1261

tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);

sys/dev/drm/i915/intel_runtime_pm.c

1263

vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);

sys/dev/drm/i915/intel_runtime_pm.c

1311

enum i915_pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;

sys/dev/drm/i915/intel_runtime_pm.c

1330

val = vlv_dpio_read(dev_priv, pipe, reg);

sys/dev/drm/i915/intel_runtime_pm.c

1434

enum i915_pipe pipe = PIPE_A;

sys/dev/drm/i915/intel_runtime_pm.c

1440

state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);

sys/dev/drm/i915/intel_runtime_pm.c

1445

WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));

sys/dev/drm/i915/intel_runtime_pm.c

1446

enabled = state == DP_SSS_PWR_ON(pipe);

sys/dev/drm/i915/intel_runtime_pm.c

1452

ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);

sys/dev/drm/i915/intel_runtime_pm.c

1464

enum i915_pipe pipe = PIPE_A;

sys/dev/drm/i915/intel_runtime_pm.c

1468

state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);

sys/dev/drm/i915/intel_runtime_pm.c

1473

((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)

sys/dev/drm/i915/intel_runtime_pm.c

1479

ctrl &= ~DP_SSC_MASK(pipe);

sys/dev/drm/i915/intel_runtime_pm.c

1480

ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);

sys/dev/drm/i915/intel_runtime_pm.c

987

enum i915_pipe pipe;

sys/dev/drm/i915/intel_runtime_pm.c

997

for_each_pipe(dev_priv, pipe) {

sys/dev/drm/i915/intel_runtime_pm.c

998

u32 val = I915_READ(DPLL(pipe));

sys/dev/drm/i915/intel_sdvo.c

1367

sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);

sys/dev/drm/i915/intel_sdvo.c

1369

sdvox |= SDVO_PIPE_SEL(crtc->pipe);

sys/dev/drm/i915/intel_sdvo.c

1405

i915_reg_t sdvo_reg, enum i915_pipe *pipe)

sys/dev/drm/i915/intel_sdvo.c

1413

*pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;

sys/dev/drm/i915/intel_sdvo.c

1415

*pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;

sys/dev/drm/i915/intel_sdvo.c

1417

*pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;

sys/dev/drm/i915/intel_sdvo.c

1423

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_sdvo.c

1432

ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);

sys/dev/drm/i915/intel_sdvo.c

1553

if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {

sys/dev/drm/i915/intel_sdvo.c

1605

intel_wait_for_vblank(dev_priv, intel_crtc->pipe);

sys/dev/drm/i915/intel_sideband.c

181

u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg)

sys/dev/drm/i915/intel_sideband.c

185

vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),

sys/dev/drm/i915/intel_sideband.c

193

pipe_name(pipe), reg, val);

sys/dev/drm/i915/intel_sideband.c

198

void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val)

sys/dev/drm/i915/intel_sideband.c

200

vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),

sys/dev/drm/i915/intel_sprite.c

1000

I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);

sys/dev/drm/i915/intel_sprite.c

1003

I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);

sys/dev/drm/i915/intel_sprite.c

1005

I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);

sys/dev/drm/i915/intel_sprite.c

1007

I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);

sys/dev/drm/i915/intel_sprite.c

1008

I915_WRITE_FW(DVSSCALE(pipe), dvsscale);

sys/dev/drm/i915/intel_sprite.c

1009

I915_WRITE_FW(DVSCNTR(pipe), dvscntr);

sys/dev/drm/i915/intel_sprite.c

1010

I915_WRITE_FW(DVSSURF(pipe),

sys/dev/drm/i915/intel_sprite.c

1012

POSTING_READ_FW(DVSSURF(pipe));

sys/dev/drm/i915/intel_sprite.c

1021

enum i915_pipe pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

1026

I915_WRITE_FW(DVSCNTR(pipe), 0);

sys/dev/drm/i915/intel_sprite.c

1028

I915_WRITE_FW(DVSSCALE(pipe), 0);

sys/dev/drm/i915/intel_sprite.c

1030

I915_WRITE_FW(DVSSURF(pipe), 0);

sys/dev/drm/i915/intel_sprite.c

1031

POSTING_READ_FW(DVSSURF(pipe));

sys/dev/drm/i915/intel_sprite.c

1038

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_sprite.c

1044

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/drm/i915/intel_sprite.c

1048

ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;

sys/dev/drm/i915/intel_sprite.c

1050

*pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

132

pipe_name(crtc->pipe));

sys/dev/drm/i915/intel_sprite.c

1457

to_intel_plane(plane)->pipe);

sys/dev/drm/i915/intel_sprite.c

1743

enum i915_pipe pipe, enum plane_id plane_id)

sys/dev/drm/i915/intel_sprite.c

1752

return pipe != PIPE_C;

sys/dev/drm/i915/intel_sprite.c

1754

return pipe != PIPE_C &&

sys/dev/drm/i915/intel_sprite.c

1761

enum i915_pipe pipe, int plane)

sys/dev/drm/i915/intel_sprite.c

1789

intel_plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe,

sys/dev/drm/i915/intel_sprite.c

1798

if (skl_plane_has_planar(dev_priv, pipe,

sys/dev/drm/i915/intel_sprite.c

1862

} else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {

sys/dev/drm/i915/intel_sprite.c

187

enum i915_pipe pipe = crtc->pipe;

sys/dev/drm/i915/intel_sprite.c

1871

intel_plane->pipe = pipe;

sys/dev/drm/i915/intel_sprite.c

1874

intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);

sys/dev/drm/i915/intel_sprite.c

1876

possible_crtcs = (1 << pipe);

sys/dev/drm/i915/intel_sprite.c

1884

"plane %d%c", plane + 2, pipe_name(pipe));

sys/dev/drm/i915/intel_sprite.c

1891

"sprite %c", sprite_name(pipe, plane));

sys/dev/drm/i915/intel_sprite.c

217

pipe_name(pipe), crtc->debug.start_vbl_count,

sys/dev/drm/i915/intel_sprite.c

227

pipe_name(pipe),

sys/dev/drm/i915/intel_sprite.c

311

enum i915_pipe pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

347

I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),

sys/dev/drm/i915/intel_sprite.c

349

I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);

sys/dev/drm/i915/intel_sprite.c

350

I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),

sys/dev/drm/i915/intel_sprite.c

352

I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),

sys/dev/drm/i915/intel_sprite.c

354

I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);

sys/dev/drm/i915/intel_sprite.c

355

I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);

sys/dev/drm/i915/intel_sprite.c

365

enum i915_pipe pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

386

I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

390

I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);

sys/dev/drm/i915/intel_sprite.c

391

I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);

sys/dev/drm/i915/intel_sprite.c

392

I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);

sys/dev/drm/i915/intel_sprite.c

395

I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);

sys/dev/drm/i915/intel_sprite.c

396

I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);

sys/dev/drm/i915/intel_sprite.c

397

I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);

sys/dev/drm/i915/intel_sprite.c

398

I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

400

I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

407

I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);

sys/dev/drm/i915/intel_sprite.c

409

I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);

sys/dev/drm/i915/intel_sprite.c

412

I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);

sys/dev/drm/i915/intel_sprite.c

413

I915_WRITE_FW(PLANE_SURF(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

415

POSTING_READ_FW(PLANE_SURF(pipe, plane_id));

sys/dev/drm/i915/intel_sprite.c

425

enum i915_pipe pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

430

I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);

sys/dev/drm/i915/intel_sprite.c

432

I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);

sys/dev/drm/i915/intel_sprite.c

433

POSTING_READ_FW(PLANE_SURF(pipe, plane_id));

sys/dev/drm/i915/intel_sprite.c

440

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_sprite.c

447

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/drm/i915/intel_sprite.c

451

ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;

sys/dev/drm/i915/intel_sprite.c

453

*pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

525

enum i915_pipe pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

552

I915_WRITE_FW(SPCLRC0(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

554

I915_WRITE_FW(SPCLRC1(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

632

enum i915_pipe pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

656

if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)

sys/dev/drm/i915/intel_sprite.c

660

I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);

sys/dev/drm/i915/intel_sprite.c

661

I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);

sys/dev/drm/i915/intel_sprite.c

662

I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);

sys/dev/drm/i915/intel_sprite.c

664

I915_WRITE_FW(SPSTRIDE(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

666

I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);

sys/dev/drm/i915/intel_sprite.c

669

I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);

sys/dev/drm/i915/intel_sprite.c

671

I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);

sys/dev/drm/i915/intel_sprite.c

673

I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);

sys/dev/drm/i915/intel_sprite.c

675

I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);

sys/dev/drm/i915/intel_sprite.c

676

I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);

sys/dev/drm/i915/intel_sprite.c

677

I915_WRITE_FW(SPSURF(pipe, plane_id),

sys/dev/drm/i915/intel_sprite.c

679

POSTING_READ_FW(SPSURF(pipe, plane_id));

sys/dev/drm/i915/intel_sprite.c

688

enum i915_pipe pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

694

I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);

sys/dev/drm/i915/intel_sprite.c

696

I915_WRITE_FW(SPSURF(pipe, plane_id), 0);

sys/dev/drm/i915/intel_sprite.c

697

POSTING_READ_FW(SPSURF(pipe, plane_id));

sys/dev/drm/i915/intel_sprite.c

704

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_sprite.c

711

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/drm/i915/intel_sprite.c

715

ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;

sys/dev/drm/i915/intel_sprite.c

717

*pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

793

enum i915_pipe pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

822

I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);

sys/dev/drm/i915/intel_sprite.c

823

I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);

sys/dev/drm/i915/intel_sprite.c

824

I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);

sys/dev/drm/i915/intel_sprite.c

827

I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);

sys/dev/drm/i915/intel_sprite.c

828

I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);

sys/dev/drm/i915/intel_sprite.c

833

I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);

sys/dev/drm/i915/intel_sprite.c

835

I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);

sys/dev/drm/i915/intel_sprite.c

837

I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);

sys/dev/drm/i915/intel_sprite.c

839

I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);

sys/dev/drm/i915/intel_sprite.c

841

I915_WRITE_FW(SPRSCALE(pipe), sprscale);

sys/dev/drm/i915/intel_sprite.c

842

I915_WRITE_FW(SPRCTL(pipe), sprctl);

sys/dev/drm/i915/intel_sprite.c

843

I915_WRITE_FW(SPRSURF(pipe),

sys/dev/drm/i915/intel_sprite.c

845

POSTING_READ_FW(SPRSURF(pipe));

sys/dev/drm/i915/intel_sprite.c

854

enum i915_pipe pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

859

I915_WRITE_FW(SPRCTL(pipe), 0);

sys/dev/drm/i915/intel_sprite.c

862

I915_WRITE_FW(SPRSCALE(pipe), 0);

sys/dev/drm/i915/intel_sprite.c

864

I915_WRITE_FW(SPRSURF(pipe), 0);

sys/dev/drm/i915/intel_sprite.c

865

POSTING_READ_FW(SPRSURF(pipe));

sys/dev/drm/i915/intel_sprite.c

872

enum i915_pipe *pipe)

sys/dev/drm/i915/intel_sprite.c

878

power_domain = POWER_DOMAIN_PIPE(plane->pipe);

sys/dev/drm/i915/intel_sprite.c

882

ret = I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;

sys/dev/drm/i915/intel_sprite.c

884

*pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

965

enum i915_pipe pipe = plane->pipe;

sys/dev/drm/i915/intel_sprite.c

994

I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);

sys/dev/drm/i915/intel_sprite.c

995

I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);

sys/dev/drm/i915/intel_sprite.c

996

I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);

sys/dev/drm/i915/intel_sprite.c

999

I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);

sys/dev/drm/i915/intel_tv.c

1031

tv_ctl |= TV_ENC_PIPE_SEL(intel_crtc->pipe);

sys/dev/drm/i915/intel_tv.c

1081

assert_pipe_disabled(dev_priv, intel_crtc->pipe);

sys/dev/drm/i915/intel_tv.c

1157

tv_ctl |= TV_ENC_PIPE_SEL(intel_crtc->pipe);

sys/dev/drm/i915/intel_tv.c

1182

intel_wait_for_vblank(dev_priv, intel_crtc->pipe);

sys/dev/drm/i915/intel_tv.c

1212

intel_wait_for_vblank(dev_priv, intel_crtc->pipe);

sys/dev/drm/i915/intel_tv.c

799

intel_tv_get_hw_state(struct intel_encoder *encoder, enum i915_pipe *pipe)

sys/dev/drm/i915/intel_tv.c

804

*pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;

sys/dev/drm/i915/intel_tv.c

819

to_intel_crtc(pipe_config->base.crtc)->pipe);

sys/dev/drm/i915/vlv_dsi.c

1019

enum i915_pipe *pipe)

sys/dev/drm/i915/vlv_dsi.c

1075

*pipe = tmp;

sys/dev/drm/i915/vlv_dsi.c

1077

*pipe = port == PORT_A ? PIPE_A : PIPE_B;

sys/dev/drm/i915/vlv_dsi.c

1414

DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));

sys/dev/drm/i915/vlv_dsi.c

1441

enum i915_pipe pipe = intel_crtc->pipe;

sys/dev/drm/i915/vlv_dsi.c

1446

tmp |= BXT_PIPE_SELECT(pipe);

sys/dev/drm/i915/vlv_dsi.c

715

temp |= crtc->pipe ?

sys/dev/drm/i915/vlv_dsi.c

804

int pipe = intel_crtc->pipe;

sys/dev/drm/i915/vlv_dsi.c

811

intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

sys/dev/drm/include/drm/drm_audio_component.h

43

int (*sync_audio_rate)(struct device *, int port, int pipe, int rate);

sys/dev/drm/include/drm/drm_audio_component.h

56

int (*get_eld)(struct device *, int port, int pipe, bool *enabled,

sys/dev/drm/include/drm/drm_audio_component.h

76

void (*pin_eld_notify)(void *audio_ptr, int port, int pipe);

sys/dev/drm/include/drm/drm_drv.h

208

u32 (*get_vblank_counter) (struct drm_device *dev, unsigned int pipe);

sys/dev/drm/include/drm/drm_drv.h

224

int (*enable_vblank) (struct drm_device *dev, unsigned int pipe);

sys/dev/drm/include/drm/drm_drv.h

235

void (*disable_vblank) (struct drm_device *dev, unsigned int pipe);

sys/dev/drm/include/drm/drm_drv.h

287

bool (*get_scanout_position) (struct drm_device *dev, unsigned int pipe,

sys/dev/drm/include/drm/drm_drv.h

335

bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe,

sys/dev/drm/include/drm/drm_gem_framebuffer_helper.h

31

int drm_gem_fb_simple_display_pipe_prepare_fb(struct drm_simple_display_pipe *pipe,

sys/dev/drm/include/drm/drm_simple_kms_helper.h

110

void (*update)(struct drm_simple_display_pipe *pipe,

sys/dev/drm/include/drm/drm_simple_kms_helper.h

123

int (*prepare_fb)(struct drm_simple_display_pipe *pipe,

sys/dev/drm/include/drm/drm_simple_kms_helper.h

133

void (*cleanup_fb)(struct drm_simple_display_pipe *pipe,

sys/dev/drm/include/drm/drm_simple_kms_helper.h

143

int (*enable_vblank)(struct drm_simple_display_pipe *pipe);

sys/dev/drm/include/drm/drm_simple_kms_helper.h

152

void (*disable_vblank)(struct drm_simple_display_pipe *pipe);

sys/dev/drm/include/drm/drm_simple_kms_helper.h

175

int drm_simple_display_pipe_attach_bridge(struct drm_simple_display_pipe *pipe,

sys/dev/drm/include/drm/drm_simple_kms_helper.h

179

struct drm_simple_display_pipe *pipe,

sys/dev/drm/include/drm/drm_simple_kms_helper.h

66

void (*enable)(struct drm_simple_display_pipe *pipe,

sys/dev/drm/include/drm/drm_simple_kms_helper.h

76

void (*disable)(struct drm_simple_display_pipe *pipe);

sys/dev/drm/include/drm/drm_simple_kms_helper.h

95

int (*check)(struct drm_simple_display_pipe *pipe,

sys/dev/drm/include/drm/drm_vblank.h

144

unsigned int pipe;

sys/dev/drm/include/drm/drm_vblank.h

189

bool drm_handle_vblank(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/include/drm/drm_vblank.h

193

void drm_wait_one_vblank(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/include/drm/drm_vblank.h

199

void drm_vblank_restore(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/include/drm/drm_vblank.h

203

unsigned int pipe, int *max_error,

sys/dev/drm/include/drm/drm_vblank.h

49

unsigned int pipe;

sys/dev/drm/include/drm/intel_lpe_audio.h

37

int pipe;

sys/dev/drm/include/uapi/drm/i915_drm.h

1277

__u32 pipe;

sys/dev/drm/include/uapi/drm/i915_drm.h

610

int pipe;

sys/dev/drm/radeon/cik.c

1837

u32 me, u32 pipe, u32 queue, u32 vmid)

sys/dev/drm/radeon/cik.c

1839

u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |

sys/dev/drm/radeon/cik.c

3532

ref_and_mask = CP2 << ring->pipe;

sys/dev/drm/radeon/cik.c

3535

ref_and_mask = CP6 << ring->pipe;

sys/dev/drm/radeon/cik.c

4174

cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/radeon/cik.c

4193

cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/radeon/cik.c

4215

cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);

sys/dev/drm/radeon/cik.c

4560

int pipe = (i < 4) ? i : (i - 4);

sys/dev/drm/radeon/cik.c

4562

cik_srbm_select(rdev, me, pipe, 0, 0);

sys/dev/drm/radeon/cik.c

4632

rdev->ring[idx].pipe,

sys/dev/drm/radeon/cik.c

7096

switch (ring->pipe) {

sys/dev/drm/radeon/cik.c

7110

DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);

sys/dev/drm/radeon/cik.c

7114

switch (ring->pipe) {

sys/dev/drm/radeon/cik.c

7128

DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);

sys/dev/drm/radeon/cik.c

7139

switch (ring->pipe) {

sys/dev/drm/radeon/cik.c

7153

DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);

sys/dev/drm/radeon/cik.c

7157

switch (ring->pipe) {

sys/dev/drm/radeon/cik.c

7171

DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);

sys/dev/drm/radeon/cik.c

7967

if ((cp1_ring->me == me_id) & (cp1_ring->pipe == pipe_id))

sys/dev/drm/radeon/cik.c

7969

if ((cp2_ring->me == me_id) & (cp2_ring->pipe == pipe_id))

sys/dev/drm/radeon/cik.c

8442

ring->pipe = 0; /* first pipe */

sys/dev/drm/radeon/cik.c

8454

ring->pipe = 0; /* first pipe */

sys/dev/drm/radeon/cypress_dpm.c

1748

u32 tmp, pipe;

sys/dev/drm/radeon/cypress_dpm.c

1765

pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;

sys/dev/drm/radeon/cypress_dpm.c

1768

(!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {

sys/dev/drm/radeon/cypress_dpm.c

1775

pipe = 0;

sys/dev/drm/radeon/cypress_dpm.c

1777

pipe = i;

sys/dev/drm/radeon/cypress_dpm.c

1780

tmp |= DCCG_DISP1_SLOW_SELECT(pipe);

sys/dev/drm/radeon/radeon.h

866

u32 pipe;

sys/dev/drm/radeon/radeon_display.c

1809

int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,

sys/dev/drm/radeon/radeon_display.c

1827

if (pipe == 0) {

sys/dev/drm/radeon/radeon_display.c

1834

if (pipe == 1) {

sys/dev/drm/radeon/radeon_display.c

1841

if (pipe == 2) {

sys/dev/drm/radeon/radeon_display.c

1848

if (pipe == 3) {

sys/dev/drm/radeon/radeon_display.c

1855

if (pipe == 4) {

sys/dev/drm/radeon/radeon_display.c

1862

if (pipe == 5) {

sys/dev/drm/radeon/radeon_display.c

1870

if (pipe == 0) {

sys/dev/drm/radeon/radeon_display.c

1875

if (pipe == 1) {

sys/dev/drm/radeon/radeon_display.c

1882

if (pipe == 0) {

sys/dev/drm/radeon/radeon_display.c

1896

if (pipe == 1) {

sys/dev/drm/radeon/radeon_display.c

1948

vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;

sys/dev/drm/radeon/radeon_drv.c

115

u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/radeon/radeon_drv.c

116

int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/radeon/radeon_drv.c

117

void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/radeon/radeon_drv.c

659

radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,

sys/dev/drm/radeon/radeon_drv.c

664

return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,

sys/dev/drm/radeon/radeon_kms.c

761

u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);

sys/dev/drm/radeon/radeon_kms.c

762

u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)

sys/dev/drm/radeon/radeon_kms.c

768

if (pipe >= rdev->num_crtc) {

sys/dev/drm/radeon/radeon_kms.c

769

DRM_ERROR("Invalid crtc %u\n", pipe);

sys/dev/drm/radeon/radeon_kms.c

781

if (rdev->mode_info.crtcs[pipe]) {

sys/dev/drm/radeon/radeon_kms.c

786

count = radeon_get_vblank_counter(rdev, pipe);

sys/dev/drm/radeon/radeon_kms.c

792

dev, pipe, GET_DISTANCE_TO_VBLANKSTART,

sys/dev/drm/radeon/radeon_kms.c

794

&rdev->mode_info.crtcs[pipe]->base.hwmode);

sys/dev/drm/radeon/radeon_kms.c

795

} while (count != radeon_get_vblank_counter(rdev, pipe));

sys/dev/drm/radeon/radeon_kms.c

803

pipe, vpos);

sys/dev/drm/radeon/radeon_kms.c

815

count = radeon_get_vblank_counter(rdev, pipe);

sys/dev/drm/radeon/radeon_mode.h

879

extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,

sys/dev/drm/radeon/si_dpm.c

3686

u32 tmp, pipe;

sys/dev/drm/radeon/si_dpm.c

3703

pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;

sys/dev/drm/radeon/si_dpm.c

3706

(!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {

sys/dev/drm/radeon/si_dpm.c

3713

pipe = 0;

sys/dev/drm/radeon/si_dpm.c

3715

pipe = i;

sys/dev/drm/radeon/si_dpm.c

3718

tmp |= DCCG_DISP1_SLOW_SELECT(pipe);

sys/kern/sys_pipe.c

1000

pipe = (struct pipe *)((intptr_t)fp->f_data & ~(intptr_t)1);

sys/kern/sys_pipe.c

1002

rpb = &pipe->bufferB;

sys/kern/sys_pipe.c

1004

rpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1057

struct pipe *pipe;

sys/kern/sys_pipe.c

1059

pipe = (struct pipe *)((intptr_t)fp->f_data & ~(intptr_t)1);

sys/kern/sys_pipe.c

1061

rpb = &pipe->bufferB;

sys/kern/sys_pipe.c

1063

rpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1073

ub->st_ctimespec = pipe->ctime;

sys/kern/sys_pipe.c

1076

ub->st_ino = pipe->inum;

sys/kern/sys_pipe.c

1091

struct pipe *pipe;

sys/kern/sys_pipe.c

1093

pipe = (struct pipe *)((intptr_t)fp->f_data & ~(intptr_t)1);

sys/kern/sys_pipe.c

1095

rpb = &pipe->bufferB;

sys/kern/sys_pipe.c

1096

wpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1098

rpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1099

wpb = &pipe->bufferB;

sys/kern/sys_pipe.c

1105

pipeclose(pipe, rpb, wpb);

sys/kern/sys_pipe.c

1118

struct pipe *pipe;

sys/kern/sys_pipe.c

1121

pipe = (struct pipe *)((intptr_t)fp->f_data & ~(intptr_t)1);

sys/kern/sys_pipe.c

1123

rpb = &pipe->bufferB;

sys/kern/sys_pipe.c

1124

wpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1126

rpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1127

wpb = &pipe->bufferB;

sys/kern/sys_pipe.c

116

SYSCTL_NODE(_kern, OID_AUTO, pipe, CTLFLAG_RW, 0, "Pipe operation");

sys/kern/sys_pipe.c

1204

pipeclose(struct pipe *pipe, struct pipebuf *rpb, struct pipebuf *wpb)

sys/kern/sys_pipe.c

1208

if (pipe == NULL)

sys/kern/sys_pipe.c

1272

if (atomic_fetchadd_int(&pipe->open_count, -1) == 1) {

sys/kern/sys_pipe.c

1279

kfree(pipe, M_PIPE);

sys/kern/sys_pipe.c

1283

pipe->next = gd->gd_pipeq;

sys/kern/sys_pipe.c

1284

gd->gd_pipeq = pipe;

sys/kern/sys_pipe.c

1295

struct pipe *pipe;

sys/kern/sys_pipe.c

1297

pipe = (struct pipe *)((intptr_t)fp->f_data & ~(intptr_t)1);

sys/kern/sys_pipe.c

1299

rpb = &pipe->bufferB;

sys/kern/sys_pipe.c

1300

wpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1302

rpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1303

wpb = &pipe->bufferB;

sys/kern/sys_pipe.c

1317

if (rpb == &pipe->bufferA)

sys/kern/sys_pipe.c

1318

kn->kn_hook = (caddr_t)(void *)((intptr_t)pipe | 0);

sys/kern/sys_pipe.c

1320

kn->kn_hook = (caddr_t)(void *)((intptr_t)pipe | 1);

sys/kern/sys_pipe.c

1332

struct pipe *pipe;

sys/kern/sys_pipe.c

1334

pipe = (struct pipe *)((intptr_t)kn->kn_hook & ~(intptr_t)1);

sys/kern/sys_pipe.c

1336

rpb = &pipe->bufferB;

sys/kern/sys_pipe.c

1337

wpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1339

rpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1340

wpb = &pipe->bufferB;

sys/kern/sys_pipe.c

1351

struct pipe *pipe;

sys/kern/sys_pipe.c

1354

pipe = (struct pipe *)((intptr_t)kn->kn_fp->f_data & ~(intptr_t)1);

sys/kern/sys_pipe.c

1356

rpb = &pipe->bufferB;

sys/kern/sys_pipe.c

1357

wpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1359

rpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1360

wpb = &pipe->bufferB;

sys/kern/sys_pipe.c

1413

struct pipe *pipe;

sys/kern/sys_pipe.c

1416

pipe = (struct pipe *)((intptr_t)kn->kn_fp->f_data & ~(intptr_t)1);

sys/kern/sys_pipe.c

1418

rpb = &pipe->bufferB;

sys/kern/sys_pipe.c

1419

wpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1421

rpb = &pipe->bufferA;

sys/kern/sys_pipe.c

1422

wpb = &pipe->bufferB;

sys/kern/sys_pipe.c

179

static void pipeclose (struct pipe *pipe,

sys/kern/sys_pipe.c

182

static int pipe_create (struct pipe **pipep);

sys/kern/sys_pipe.c

282

struct pipe *pipe;

sys/kern/sys_pipe.c

285

pipe = NULL;

sys/kern/sys_pipe.c

286

if (pipe_create(&pipe)) {

sys/kern/sys_pipe.c

287

pipeclose(pipe, &pipe->bufferA, &pipe->bufferB);

sys/kern/sys_pipe.c

288

pipeclose(pipe, &pipe->bufferB, &pipe->bufferA);

sys/kern/sys_pipe.c

294

pipeclose(pipe, &pipe->bufferA, &pipe->bufferB);

sys/kern/sys_pipe.c

295

pipeclose(pipe, &pipe->bufferB, &pipe->bufferA);

sys/kern/sys_pipe.c

309

rf->f_data = (void *)((intptr_t)pipe | 0);

sys/kern/sys_pipe.c

323

pipeclose(pipe, &pipe->bufferB, &pipe->bufferA);

sys/kern/sys_pipe.c

329

wf->f_data = (void *)((intptr_t)pipe | 1);

sys/kern/sys_pipe.c

360

pipespace(struct pipe *pipe, struct pipebuf *pb, size_t size)

sys/kern/sys_pipe.c

415

pipe_create(struct pipe **pipep)

sys/kern/sys_pipe.c

418

struct pipe *pipe;

sys/kern/sys_pipe.c

421

if ((pipe = gd->gd_pipeq) != NULL) {

sys/kern/sys_pipe.c

422

gd->gd_pipeq = pipe->next;

sys/kern/sys_pipe.c

424

pipe->next = NULL;

sys/kern/sys_pipe.c

426

pipe = kmalloc(sizeof(*pipe), M_PIPE, M_WAITOK | M_ZERO);

sys/kern/sys_pipe.c

427

pipe->inum = gd->gd_anoninum++ * ncpus + gd->gd_cpuid + 2;

sys/kern/sys_pipe.c

428

lwkt_token_init(&pipe->bufferA.rlock, "piper");

sys/kern/sys_pipe.c

429

lwkt_token_init(&pipe->bufferA.wlock, "pipew");

sys/kern/sys_pipe.c

430

lwkt_token_init(&pipe->bufferB.rlock, "piper");

sys/kern/sys_pipe.c

431

lwkt_token_init(&pipe->bufferB.wlock, "pipew");

sys/kern/sys_pipe.c

433

*pipep = pipe;

sys/kern/sys_pipe.c

434

if ((error = pipespace(pipe, &pipe->bufferA, pipe_size)) != 0) {

sys/kern/sys_pipe.c

437

if ((error = pipespace(pipe, &pipe->bufferB, pipe_size)) != 0) {

sys/kern/sys_pipe.c

440

vfs_timestamp(&pipe->ctime);

sys/kern/sys_pipe.c

441

pipe->bufferA.atime = pipe->ctime;

sys/kern/sys_pipe.c

442

pipe->bufferA.mtime = pipe->ctime;

sys/kern/sys_pipe.c

443

pipe->bufferB.atime = pipe->ctime;

sys/kern/sys_pipe.c

444

pipe->bufferB.mtime = pipe->ctime;

sys/kern/sys_pipe.c

445

pipe->open_count = 2;

sys/kern/sys_pipe.c

458

struct pipe *pipe;

sys/kern/sys_pipe.c

469

pipe = (struct pipe *)((intptr_t)fp->f_data & ~(intptr_t)1);

sys/kern/sys_pipe.c

471

rpb = &pipe->bufferB;

sys/kern/sys_pipe.c

472

wpb = &pipe->bufferA;

sys/kern/sys_pipe.c

474

rpb = &pipe->bufferA;

sys/kern/sys_pipe.c

475

wpb = &pipe->bufferB;

sys/kern/sys_pipe.c

705

struct pipe *pipe;

sys/kern/sys_pipe.c

715

pipe = (struct pipe *)((intptr_t)fp->f_data & ~(intptr_t)1);

sys/kern/sys_pipe.c

717

rpb = &pipe->bufferB;

sys/kern/sys_pipe.c

718

wpb = &pipe->bufferA;

sys/kern/sys_pipe.c

720

rpb = &pipe->bufferA;

sys/kern/sys_pipe.c

721

wpb = &pipe->bufferB;

sys/kern/sys_pipe.c

997

struct pipe *pipe;

sys/net/dummynet/ip_dummynet.c

1038

struct dn_pipe *pipe;

sys/net/dummynet/ip_dummynet.c

1056

pipe = fs->pipe;

sys/net/dummynet/ip_dummynet.c

1057

if (pipe == NULL) { /* Must be a queue, try find a matching pipe */

sys/net/dummynet/ip_dummynet.c

1058

pipe = dn_find_pipe(fs->parent_nr);

sys/net/dummynet/ip_dummynet.c

1059

if (pipe != NULL) {

sys/net/dummynet/ip_dummynet.c

1060

fs->pipe = pipe;

sys/net/dummynet/ip_dummynet.c

1110

if (pipe->bandwidth)

sys/net/dummynet/ip_dummynet.c

1111

t = SET_TICKS(pkt, q, pipe);

sys/net/dummynet/ip_dummynet.c

1130

q->S = pipe->V;

sys/net/dummynet/ip_dummynet.c

1131

pipe->sum += fs->weight; /* Add weight of new queue */

sys/net/dummynet/ip_dummynet.c

1133

heap_extract(&pipe->idle_heap, q);

sys/net/dummynet/ip_dummynet.c

1134

q->S = MAX64(q->F, pipe->V);

sys/net/dummynet/ip_dummynet.c

1138

if (pipe->not_eligible_heap.elements == 0 &&

sys/net/dummynet/ip_dummynet.c

1139

pipe->scheduler_heap.elements == 0)

sys/net/dummynet/ip_dummynet.c

1140

pipe->V = MAX64(q->S, pipe->V);

sys/net/dummynet/ip_dummynet.c

1157

if (DN_KEY_GT(q->S, pipe->V)) { /* Not eligible */

sys/net/dummynet/ip_dummynet.c

1158

if (pipe->scheduler_heap.elements == 0)

sys/net/dummynet/ip_dummynet.c

1160

heap_insert(&pipe->not_eligible_heap, q->S, q);

sys/net/dummynet/ip_dummynet.c

1162

heap_insert(&pipe->scheduler_heap, q->F, q);

sys/net/dummynet/ip_dummynet.c

1163

if (pipe->numbytes >= 0) { /* Pipe is idle */

sys/net/dummynet/ip_dummynet.c

1164

if (pipe->scheduler_heap.elements != 1)

sys/net/dummynet/ip_dummynet.c

1167

pipe->pipe_nr, (int)(q->F >> MY_M));

sys/net/dummynet/ip_dummynet.c

1168

pipe->sched_time = curr_time;

sys/net/dummynet/ip_dummynet.c

1169

ready_event_wfq(pipe);

sys/net/dummynet/ip_dummynet.c

1236

if (fs->pipe == NULL || (fs->pipe && fs != &fs->pipe->fs))

sys/net/dummynet/ip_dummynet.c

1247

purge_pipe(struct dn_pipe *pipe)

sys/net/dummynet/ip_dummynet.c

1251

purge_flow_set(&pipe->fs, 1);

sys/net/dummynet/ip_dummynet.c

1253

while ((pkt = TAILQ_FIRST(&pipe->p_queue)) != NULL) {

sys/net/dummynet/ip_dummynet.c

1254

TAILQ_REMOVE(&pipe->p_queue, pkt, dn_next);

sys/net/dummynet/ip_dummynet.c

1258

heap_free(&pipe->scheduler_heap);

sys/net/dummynet/ip_dummynet.c

1259

heap_free(&pipe->not_eligible_heap);

sys/net/dummynet/ip_dummynet.c

1260

heap_free(&pipe->idle_heap);

sys/net/dummynet/ip_dummynet.c

1494

x->fs.pipe = x;

sys/net/dummynet/ip_dummynet.c

1630

struct dn_pipe *pipe = pipe0;

sys/net/dummynet/ip_dummynet.c

1632

if (fs->pipe == pipe) {

sys/net/dummynet/ip_dummynet.c

1634

pipe->pipe_nr, fs->fs_nr);

sys/net/dummynet/ip_dummynet.c

1635

fs->pipe = NULL;

sys/net/dummynet/ip_dummynet.c

1692

if ((p = fs->pipe) != NULL) {

sys/net/dummynet/ip_dummynet.c

1801

dn_calc_pipe_size_cb(struct dn_pipe *pipe, void *sz)

sys/net/dummynet/ip_dummynet.c

1806

pipe->fs.rq_elements * sizeof(struct dn_ioc_flowqueue);

sys/net/dummynet/ip_dummynet.c

1819

dn_copyout_pipe_cb(struct dn_pipe *pipe, void *bp0)

sys/net/dummynet/ip_dummynet.c

1827

dn_copy_flowset(&pipe->fs, &ioc_pipe->fs, DN_IS_PIPE);

sys/net/dummynet/ip_dummynet.c

1832

ioc_pipe->bandwidth = pipe->bandwidth;

sys/net/dummynet/ip_dummynet.c

1833

ioc_pipe->pipe_nr = pipe->pipe_nr;

sys/net/dummynet/ip_dummynet.c

1834

ioc_pipe->V = pipe->V;

sys/net/dummynet/ip_dummynet.c

1836

ioc_pipe->delay = (pipe->delay * 1000) / dn_hz;

sys/net/dummynet/ip_dummynet.c

1842

*bp = dn_copy_flowqueues(&pipe->fs, *bp);

sys/net/dummynet/ip_dummynet.c

404

transmit_event(struct dn_pipe *pipe)

sys/net/dummynet/ip_dummynet.c

408

while ((pkt = TAILQ_FIRST(&pipe->p_queue)) &&

sys/net/dummynet/ip_dummynet.c

410

TAILQ_REMOVE(&pipe->p_queue, pkt, dn_next);

sys/net/dummynet/ip_dummynet.c

417

if ((pkt = TAILQ_FIRST(&pipe->p_queue)) != NULL) {

sys/net/dummynet/ip_dummynet.c

422

heap_insert(&extract_heap, pkt->output_time, pipe);

sys/net/dummynet/ip_dummynet.c

463

struct dn_pipe *p = q->fs->pipe;

sys/net/dummynet/ip_dummynet.c

642

dn_expire_pipe_cb(struct dn_pipe *pipe, void *dummy __unused)

sys/net/dummynet/ip_dummynet.c

644

if (pipe->idle_heap.elements > 0 &&

sys/net/dummynet/ip_dummynet.c

645

DN_KEY_LT(pipe->idle_heap.p[0].key, pipe->V)) {

sys/net/dummynet/ip_dummynet.c

646

struct dn_flow_queue *q = pipe->idle_heap.p[0].object;

sys/net/dummynet/ip_dummynet.c

648

heap_extract(&pipe->idle_heap, NULL);

sys/net/dummynet/ip_dummynet.c

650

pipe->sum -= q->fs->weight;

sys/net/dummynet/ip_dummynet.c

952

struct dn_pipe *pipe, *pipe_next;

sys/net/dummynet/ip_dummynet.c

954

LIST_FOREACH_MUTABLE(pipe, pipe_hdr, p_link, pipe_next)

sys/net/dummynet/ip_dummynet.c

955

func(pipe, arg);

sys/net/dummynet/ip_dummynet.h

269

struct dn_pipe *pipe; /* pointer to parent pipe */

sys/net/dummynet3/ip_dummynet3.c

1057

struct dn_pipe *pipe;

sys/net/dummynet3/ip_dummynet3.c

1075

pipe = fs->pipe;

sys/net/dummynet3/ip_dummynet3.c

1076

if (pipe == NULL) { /* Must be a queue, try find a matching pipe */

sys/net/dummynet3/ip_dummynet3.c

1077

pipe = dn_find_pipe(fs->parent_nr);

sys/net/dummynet3/ip_dummynet3.c

1078

if (pipe != NULL) {

sys/net/dummynet3/ip_dummynet3.c

1079

fs->pipe = pipe;

sys/net/dummynet3/ip_dummynet3.c

1129

if (pipe->bandwidth)

sys/net/dummynet3/ip_dummynet3.c

1130

t = SET_TICKS(pkt, q, pipe);

sys/net/dummynet3/ip_dummynet3.c

1149

q->S = pipe->V;

sys/net/dummynet3/ip_dummynet3.c

1150

pipe->sum += fs->weight; /* Add weight of new queue */

sys/net/dummynet3/ip_dummynet3.c

1152

heap_extract(&pipe->idle_heap, q);

sys/net/dummynet3/ip_dummynet3.c

1153

q->S = MAX64(q->F, pipe->V);

sys/net/dummynet3/ip_dummynet3.c

1157

if (pipe->not_eligible_heap.elements == 0 &&

sys/net/dummynet3/ip_dummynet3.c

1158

pipe->scheduler_heap.elements == 0)

sys/net/dummynet3/ip_dummynet3.c

1159

pipe->V = MAX64(q->S, pipe->V);

sys/net/dummynet3/ip_dummynet3.c

1176

if (DN_KEY_GT(q->S, pipe->V)) { /* Not eligible */

sys/net/dummynet3/ip_dummynet3.c

1177

if (pipe->scheduler_heap.elements == 0)

sys/net/dummynet3/ip_dummynet3.c

1179

heap_insert(&pipe->not_eligible_heap, q->S, q);

sys/net/dummynet3/ip_dummynet3.c

1181

heap_insert(&pipe->scheduler_heap, q->F, q);

sys/net/dummynet3/ip_dummynet3.c

1182

if (pipe->numbytes >= 0) { /* Pipe is idle */

sys/net/dummynet3/ip_dummynet3.c

1183

if (pipe->scheduler_heap.elements != 1)

sys/net/dummynet3/ip_dummynet3.c

1186

pipe->pipe_nr, (int)(q->F >> MY_M));

sys/net/dummynet3/ip_dummynet3.c

1187

pipe->sched_time = curr_time;

sys/net/dummynet3/ip_dummynet3.c

1188

ready_event_wfq(pipe);

sys/net/dummynet3/ip_dummynet3.c

1255

if (fs->pipe == NULL || (fs->pipe && fs != &fs->pipe->fs))

sys/net/dummynet3/ip_dummynet3.c

1266

purge_pipe(struct dn_pipe *pipe)

sys/net/dummynet3/ip_dummynet3.c

1270

purge_flow_set(&pipe->fs, 1);

sys/net/dummynet3/ip_dummynet3.c

1272

while ((pkt = TAILQ_FIRST(&pipe->p_queue)) != NULL) {

sys/net/dummynet3/ip_dummynet3.c

1273

TAILQ_REMOVE(&pipe->p_queue, pkt, dn_next);

sys/net/dummynet3/ip_dummynet3.c

1277

heap_free(&pipe->scheduler_heap);

sys/net/dummynet3/ip_dummynet3.c

1278

heap_free(&pipe->not_eligible_heap);

sys/net/dummynet3/ip_dummynet3.c

1279

heap_free(&pipe->idle_heap);

sys/net/dummynet3/ip_dummynet3.c

1497

x->fs.pipe = x;

sys/net/dummynet3/ip_dummynet3.c

1621

struct dn_pipe *pipe = pipe0;

sys/net/dummynet3/ip_dummynet3.c

1623

if (fs->pipe == pipe) {

sys/net/dummynet3/ip_dummynet3.c

1625

pipe->pipe_nr, fs->fs_nr);

sys/net/dummynet3/ip_dummynet3.c

1626

fs->pipe = NULL;

sys/net/dummynet3/ip_dummynet3.c

1679

if ((p = fs->pipe) != NULL) {

sys/net/dummynet3/ip_dummynet3.c

1780

dn_calc_pipe_size_cb(struct dn_pipe *pipe, void *sz)

sys/net/dummynet3/ip_dummynet3.c

1785

pipe->fs.rq_elements * sizeof(struct dn_ioc_flowqueue);

sys/net/dummynet3/ip_dummynet3.c

1798

dn_copyout_pipe_cb(struct dn_pipe *pipe, void *bp0)

sys/net/dummynet3/ip_dummynet3.c

1806

dn_copy_flowset(&pipe->fs, &ioc_pipe->fs, DN_IS_PIPE);

sys/net/dummynet3/ip_dummynet3.c

1811

ioc_pipe->bandwidth = pipe->bandwidth;

sys/net/dummynet3/ip_dummynet3.c

1812

ioc_pipe->pipe_nr = pipe->pipe_nr;

sys/net/dummynet3/ip_dummynet3.c

1813

ioc_pipe->V = pipe->V;

sys/net/dummynet3/ip_dummynet3.c

1815

ioc_pipe->delay = (pipe->delay * 1000) / dn_hz;

sys/net/dummynet3/ip_dummynet3.c

1821

*bp = dn_copy_flowqueues(&pipe->fs, *bp);

sys/net/dummynet3/ip_dummynet3.c

423

transmit_event(struct dn_pipe *pipe)

sys/net/dummynet3/ip_dummynet3.c

427

while ((pkt = TAILQ_FIRST(&pipe->p_queue)) &&

sys/net/dummynet3/ip_dummynet3.c

429

TAILQ_REMOVE(&pipe->p_queue, pkt, dn_next);

sys/net/dummynet3/ip_dummynet3.c

436

if ((pkt = TAILQ_FIRST(&pipe->p_queue)) != NULL) {

sys/net/dummynet3/ip_dummynet3.c

441

heap_insert(&extract_heap, pkt->output_time, pipe);

sys/net/dummynet3/ip_dummynet3.c

482

struct dn_pipe *p = q->fs->pipe;

sys/net/dummynet3/ip_dummynet3.c

661

dn_expire_pipe_cb(struct dn_pipe *pipe, void *dummy __unused)

sys/net/dummynet3/ip_dummynet3.c

663

if (pipe->idle_heap.elements > 0 &&

sys/net/dummynet3/ip_dummynet3.c

664

DN_KEY_LT(pipe->idle_heap.p[0].key, pipe->V)) {

sys/net/dummynet3/ip_dummynet3.c

665

struct dn_flow_queue *q = pipe->idle_heap.p[0].object;

sys/net/dummynet3/ip_dummynet3.c

667

heap_extract(&pipe->idle_heap, NULL);

sys/net/dummynet3/ip_dummynet3.c

669

pipe->sum -= q->fs->weight;

sys/net/dummynet3/ip_dummynet3.c

971

struct dn_pipe *pipe, *pipe_next;

sys/net/dummynet3/ip_dummynet3.c

973

LIST_FOREACH_MUTABLE(pipe, pipe_hdr, p_link, pipe_next)

sys/net/dummynet3/ip_dummynet3.c

974

func(pipe, arg);

sys/net/dummynet3/ip_dummynet3.h

284

struct dn_pipe *pipe; /* pointer to parent pipe */

sys/netinet/tcp_input.c

3240

uint32_t pipe;

sys/netinet/tcp_input.c

3258

pipe = tcp_sack_compute_pipe(tp);

sys/netinet/tcp_input.c

3259

while (((tcp_seq_diff_t)(ocwnd - pipe) >= (tcp_seq_diff_t)tp->t_maxseg

sys/netinet/tcp_input.c

3307

pipe += sent;

sys/netinet/tcp_input.c

3342

uint32_t pipe, sent;

sys/netinet/tcp_input.c

3348

pipe = tcp_sack_compute_pipe(tp);

sys/netinet/tcp_input.c

3349

cwnd_left = (tcp_seq_diff_t)(ocwnd - pipe);

sys/sys/globaldata.h

127

struct pipe;

sys/sys/globaldata.h

176

struct pipe *gd_pipeq; /* cache pipe structures */

sys/sys/pipe.h

95

struct pipe *next;

sys/sys/sysunion.h

52

struct pipe_args pipe;

sys/vfs/hammer2/hammer2.h

1888

void hammer2_lwinprog_wait(hammer2_pfs_t *pmp, int pipe);

test/interbench/interbench.c

1390

if (pipe(pype) == -1)

test/libpthread/mutex_d.c

1482

assert (pipe (pipefd) == 0);

test/sysperf/pipe1.c

22

if (pipe(fds)) {

test/sysperf/pipe2.c

59

if (pipe(fds)) {

test/sysperf/pipe900k.c

37

pipe(fdsbeg);

test/sysperf/pipe900k.c

48

pipe(fdsend);

test/sysperf/pipe900k.c

73

pipe(fdsend);

test/testcases/io/pselect_1/pselect_1.c

62

r = pipe(des);

test/testcases/io/select_1/select_1.c

60

r = pipe(des);

test/testcases/posixipc/common/common.c

203

if (pipe(pfd) < 0) {

tools/tools/netrate/netperf/tcp_cc/tcp_cc.c

84

if (pipe(instance[i].pipes) < 0)

tools/tools/netrate/netperf/tcp_stream/tcp_stream.c

185

if (pipe(instance[i].pipes) < 0)

usr.bin/bc/bc.y

1136

if (pipe(p) == -1)

usr.bin/calendar/io.c

660

if (pipe(pdes) < 0) {

usr.bin/fstat/fstat.c

143

static void pipetrans(struct pipe *, int, int);

usr.bin/fstat/fstat.c

374

pipetrans((struct pipe *)file.f_data, i,

usr.bin/fstat/fstat.c

803

pipetrans(struct pipe *pi, int i, int flag)

usr.bin/fstat/fstat.c

805

struct pipe pip;

usr.bin/fstat/fstat.c

827

if (!kread(pi, &pip, sizeof(struct pipe))) {

usr.bin/m4/gnum4.c

617

if (pipe(p) == -1)

usr.bin/mail/fio.c

364

if (pipe(pivec) < 0) {

usr.bin/mail/popen.c

102

if (pipe(p) < 0)

usr.bin/mail/popen.c

150

if (fp_head->pipe)

usr.bin/mail/popen.c

157

register_file(FILE *fp, int pipe, int pid)

usr.bin/mail/popen.c

164

fpp->pipe = pipe;

usr.bin/mail/popen.c

44

int pipe;

usr.bin/newkey/update.c

154

if (pipe(pdto) < 0) {

usr.bin/newkey/update.c

157

if (pipe(pdfrom) < 0) {

usr.bin/rpcgen/rpc_main.c

298

pipe(pd);

usr.bin/sdiff/sdiff.c

379

if (pipe(fd))

usr.bin/su/su.c

428

if (pipe(fds) == -1) {

usr.bin/tip/cmds.c

314

if (pipe(pdes)) {

usr.bin/tip/cmds.c

961

if (pipe(pivec) < 0) {

usr.bin/tip/tip.c

206

pipe(fildes); pipe(repdes);

usr.bin/vknet/vknet.c

131

if (pipe(fds) < 0) {

usr.sbin/autofs/popen.c

86

error = pipe(outfds);

usr.sbin/cron/cron/do_command.c

152

pipe(stdin_pipe); /* child's stdin */

usr.sbin/cron/cron/do_command.c

153

pipe(stdout_pipe); /* child's stdout */

usr.sbin/cron/cron/popen.c

81

if (pipe(pdes) < 0)

usr.sbin/daemon/daemon.c

275

if (pipe(pfd))

usr.sbin/installer/libaura/popen.c

97

if (pipe(pdes) < 0)

usr.sbin/lpr/lpd/printjob.c

1423

pipe(p);

usr.sbin/lpr/lpd/printjob.c

1662

pipe(p);

usr.sbin/lpr/lpd/printjob.c

649

pipe(p);

usr.sbin/makefs/hammer2/hammer2.h

1952

void hammer2_lwinprog_wait(hammer2_pfs_t *pmp, int pipe);

usr.sbin/ppp/bundle.c

1730

if (pipe(fds) == -1) {

usr.sbin/ppp/bundle.c

1744

if (pipe(fds) == -1) {

usr.sbin/ppp/chap.c

268

if (pipe(in) == -1) {

usr.sbin/ppp/chap.c

273

if (pipe(out) == -1) {

usr.sbin/ppp/chat.c

724

if (pipe(fids) < 0) {

usr.sbin/ppp/exec.c

128

if (pipe(pidpipe) == -1) {

usr.sbin/ppp/main.c

438

if (sw.mode == PHYS_BACKGROUND && pipe(bgpipe)) {

usr.sbin/rpc.ypupdated/update.c

150

if (pipe(pdto) < 0) {

usr.sbin/rpc.ypupdated/update.c

153

if (pipe(pdfrom) < 0) {

usr.sbin/syslogd/syslogd.c

2474

if (pipe(pfd) == -1)

usr.sbin/uefisign/uefisign.c

395

error = pipe(pipefds);

usr.sbin/ypbind/ypbind.c

650

if (pipe(ypdb->dom_pipe_fds) < 0) {