pci_cfgregread
return(pci_cfgregread(bus, slot, func, reg, bytes));
vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
u_int32_t pci_cfgregread(int bus, int slot, int func, int reg, int bytes);
ctrl = pci_cfgregread(bus, slot, func, SNB_GMCH_CTRL, 2);
ctrl = pci_cfgregread(bus, slot, func, SNB_GMCH_CTRL, 2);
ctrl = pci_cfgregread(bus, slot, func, SNB_GMCH_CTRL, 2);
ctrl = pci_cfgregread(bus, slot, func, SNB_GMCH_CTRL, 2);
vendor = pci_cfgregread(bus, slot, func, PCIR_VENDOR, 2);
class = pci_cfgregread(bus, slot, func, PCIR_SUBCLASS, 2);
device = pci_cfgregread(bus, slot, func, PCIR_DEVICE, 2);
ctrl = pci_cfgregread(bus, slot, func, INTEL_BSM, 4);
ctrl = pci_cfgregread(bus, slot, func, INTEL_GEN11_BSM_DW0, 4);
val |= (uint64_t)pci_cfgregread(
ctrl = pci_cfgregread(0, 0, 0, I830_GMCH_CTRL, 2);
*Value = pci_cfgregread(PciId->Bus, PciId->Device,
value = pci_cfgregread(bus, device, 0, PCIR_HDRTYPE, 1);
value = pci_cfgregread(bus, device, func, PCIR_DEVVENDOR, 4);
value = pci_cfgregread(bus, device, func, PCIR_INTPIN, 1);
value = pci_cfgregread(bus, device, func, PCIR_INTLINE, 1);
if (host_pcib_get_busno(pci_cfgregread, 0, slot, func, &busno) == 0)
return (pci_cfgregread(bus, slot, func, reg, bytes));
if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
(pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
devid = pci_cfgregread(0, i, 3, 0, 4);
(pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
(pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
(pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
extern uint32_t pci_cfgregread(int, int, int, int, int);
pci_cfgregread(PCIBUS_X3400UC, PCISLOT_X3400UC_MC, \
pci_cfgregread(PCIBUS_X3400UC, PCISLOT_X3400UC_MC, \
pci_cfgregread(PCIBUS_X3400UC, PCISLOT_X3400UC_MCT2, \
pci_cfgregread(PCIBUS_X3400UC, PCISLOT_X3400UC_MCT2, \
devid = pci_cfgregread(0, 4, 2, PCIR_DEVVENDOR, 4);
if ((pci_cfgregread(pci_get_bus(dev),
return (HPT_U8)pci_cfgregread(bus, dev, func, reg, 1);
return (HPT_U32)pci_cfgregread(bus, dev, func, reg, 4);