outw
const_DES_cblock *outw, int enc)
in2 = &(*outw)[0];
memcpy(&data(ctx)->outw[0], &key[16], 8);
&data(ctx)->outw, ctx->encrypt);
&data(ctx)->outw, ctx->encrypt);
DES_cblock outw;
const_DES_cblock *inw,const_DES_cblock *outw,int enc);
outw(port, data);
outw(bsh + offset, value);
outw(addr, value);
outw(addr, value);
outw(addr2, inw(addr1));
outw(addr2, inw(addr1));
void outw(u_int port, u_short data);
outw(GDCIDX, 0x0805); /* read mode 1, write mode 0 */
outw(GDCIDX, 0x0001); /* set/reset enable */
outw(GDCIDX, 0x0002); /* color compare */
outw(GDCIDX, 0x0007); /* color don't care */
outw(GDCIDX, 0xff08); /* bit mask */
outw(GDCIDX, 0x0803); /* data rotate/function select (and) */
outw(GDCIDX, 0x1003); /* data rotate/function select (or) */
outw(GDCIDX, 0x0005); /* read mode 0, write mode 0 */
outw(GDCIDX, 0x0003); /* data rotate/function select */
outw(GDCIDX, 0x0005); /* read mode 0, write mode 0 */
outw(GDCIDX, 0x0003); /* data rotate/function select */
outw(GDCIDX, 0x0f01); /* set/reset enable */
outw(GDCIDX, 0xff08); /* bit mask */
outw(GDCIDX, (color << 8) | 0x00); /* set/reset */
outw(GDCIDX, 0x0000); /* set/reset */
outw(GDCIDX, 0x0001); /* set/reset enable */
outw(GDCIDX, 0x0305); /* read mode 0, write mode 3 */
outw(GDCIDX, 0x0003); /* data rotate/function select */
outw(GDCIDX, 0x0f01); /* set/reset enable */
outw(GDCIDX, 0xff08); /* bit mask */
outw(GDCIDX, 0x0005); /* read mode 0, write mode 0 */
outw(GDCIDX, bg | 0x00); /* set/reset */
outw(GDCIDX, 0x0305); /* read mode 0, write mode 3 */
outw(GDCIDX, col1 | 0x00); /* set/reset */
outw(GDCIDX, 0x0005); /* read mode 0, write mode 0 */
outw(GDCIDX, 0x0000); /* set/reset */
outw(GDCIDX, 0x0001); /* set/reset enable */
outw(GDCIDX, 0x0005); /* read mode 0, write mode 0 */
outw(GDCIDX, 0x0003); /* data rotate/function select */
outw(GDCIDX, 0x0f01); /* set/reset enable */
outw(GDCIDX, col | 0x00); /* set/reset */
outw(GDCIDX, 0xff08); /* bit mask */
outw(GDCIDX, col | 0x00); /* set/reset */
outw(GDCIDX, (*f << 8) | 0x08); /* bit mask */
outw(GDCIDX, 0x0000); /* set/reset */
outw(GDCIDX, 0x0001); /* set/reset enable */
outw(GDCIDX, 0xff08); /* bit mask */
outw(BASE + MMU_CMD_REG_W, MMUCR_RELEASE);
outw(BASE + RECV_CONTROL_REG_W, 0x0000);
outw(BASE + TXMIT_CONTROL_REG_W, 0x0000);
outw(ioaddr + BANK_SELECT_REG_W, 0x0000);
outw(ioaddr + BANK_SELECT_REG_W, 0x0001);
outw(ioaddr + BANK_SELECT_REG_W, 0x3);
outw(BASE + MULTICAST1_REG_W,
outw(BASE + MULTICAST2_REG_W,
outw(BASE + MULTICAST3_REG_W,
outw(BASE + MULTICAST4_REG_W,
outw(BASE + RECV_CONTROL_REG_W, flags);
outw(BASE + IAR_ADDR0_REG_W + j * 2, w);
outw(BASE + RECV_CONTROL_REG_W, RCR_SOFTRESET);
outw(BASE + RECV_CONTROL_REG_W, 0x0000);
outw(BASE + TXMIT_CONTROL_REG_W, 0x0000);
outw(BASE + CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
outw(BASE + CONFIG_REG_W, flags);
outw(BASE + MMU_CMD_REG_W, MMUCR_RESET);
outw(BASE + TXMIT_CONTROL_REG_W, flags);
outw(BASE + MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000);
outw(BASE + DATA_REG_W, 0);
outw(BASE + DATA_REG_W, 0);
outw(BASE + DATA_REG_W, 0);
outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE);
outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT);
outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000);
outw(BASE + DATA_REG_W, 0);
outw(BASE + DATA_REG_W, 0);
outw(BASE + DATA_REG_W, 0);
outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE);
outw(BASE + POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE);
outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT);
outw(BASE + POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
#define SMC_SELECT_BANK(x) { outw( BASE + BANK_SELECT_REG_W, (x) ); }
void os_outw (void *port, HPT_U16 value) { outw((unsigned)(HPT_UPTR)port, (value)); }
void os_outw (void *port, HPT_U16 value) { outw((unsigned)(HPT_UPTR)port, (value)); }
outw(GDCIDX, (0x8000 >> bofs) | 0x08); /* bit mask */
outw(GDCIDX, (val << 8) | 0x00); /* set/reset */
outw(GDCIDX, 0x0f01); /* set/reset enable */
outw(TSIDX, 0x0102); /* unmask plane #0 */
outw(TSIDX, 0x0402);
outw(TSIDX, 0x0704);
outw(GDCIDX, 0x0204);
outw(GDCIDX, 0x0005);
outw(GDCIDX, 0x0406); /* addr = a0000, 64kb */
outw(TSIDX, 0x0002 | (buf[0] << 8));
outw(TSIDX, 0x0004 | (buf[1] << 8));
outw(GDCIDX, 0x0004 | (buf[2] << 8));
outw(GDCIDX, 0x0005 | (buf[3] << 8));
outw(GDCIDX, 0x0006 | (((buf[4] & 0x03) | 0x0c)<<8));
outw(GDCIDX, 0x0005); /* read mode 0, write mode 0 */
outw(GDCIDX, 0x0003); /* data rotate/function select */
outw(GDCIDX, 0x0f01); /* set/reset enable */
outw(GDCIDX, 0xff08); /* bit mask */
outw(GDCIDX, (val << 8) | 0x00); /* set/reset */
outw(GDCIDX, 0x0000); /* set/reset */
outw(GDCIDX, 0x0001); /* set/reset enable */