bin/sh/miscbltin.c

524

int optc, what;

bin/sh/miscbltin.c

528

while ((optc = nextopt("HSatfdsmcnuvlbpwko")) != '\0')

bin/sh/miscbltin.c

529

switch (optc) {

bin/sh/miscbltin.c

540

what = optc;

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

104

optc1_apply_front_porch_workaround(optc, &patched_crtc_timing);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1114

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1120

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1127

optc1_get_position(optc, &position);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1133

static void optc1_enable_stereo(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1136

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1166

void optc1_program_stereo(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1170

optc1_enable_stereo(optc, timing, flags);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1172

optc1_disable_stereo(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1176

bool optc1_is_stereo_left_eye(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1180

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1192

void optc1_read_otg_state(struct optc *optc1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

122

vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1242

bool optc1_get_otg_active_size(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1251

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1273

void optc1_clear_optc_underflow(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1275

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1280

void optc1_tg_init(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1282

optc1_set_blank_data_double_buffer(optc, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1283

optc1_clear_optc_underflow(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1286

bool optc1_is_tg_enabled(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1288

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1297

bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1299

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1309

bool optc1_configure_crc(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1312

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1315

if (!optc1_is_tg_enabled(optc))

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

132

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1353

bool optc1_get_crc(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1357

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

137

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1415

void dcn10_timing_generator_init(struct optc *optc1)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

145

uint32_t vsync_line = get_start_vline(optc, dc_crtc_timing);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

173

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

190

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

193

optc1_apply_front_porch_workaround(optc, &patched_crtc_timing);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

276

vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

292

if (optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT ||

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

293

optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

294

optc->dlg_otg_param.signal == SIGNAL_TYPE_EDP) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

300

if (optc->dlg_otg_param.vstartup_start > asic_blank_end)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

301

v_fp2 = optc->dlg_otg_param.vstartup_start > asic_blank_end;

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

308

if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

328

optc1_program_global_sync(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

348

void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

350

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

362

static void optc1_unblank_crtc(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

364

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

374

optc1_set_blank_data_double_buffer(optc, true);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

386

static void optc1_blank_crtc(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

388

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

394

optc1_set_blank_data_double_buffer(optc, false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

397

void optc1_set_blank(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

401

optc1_blank_crtc(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

403

optc1_unblank_crtc(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

406

bool optc1_is_blanked(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

408

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

419

void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

421

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

454

static bool optc1_enable_crtc(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

460

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

466

OPTC_SRC_SEL, optc->inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

481

bool optc1_disable_crtc(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

483

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

50

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

505

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

508

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

517

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

523

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

586

uint32_t optc1_get_vblank_counter(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

588

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

597

void optc1_lock(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

599

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

602

OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

607

if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

613

void optc1_unlock(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

615

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

621

void optc1_get_position(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

624

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

63

struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

634

bool optc1_is_counter_moving(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

638

optc->funcs->get_position(optc, &position1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

639

optc->funcs->get_position(optc, &position2);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

649

struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

65

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

651

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

663

void optc1_disable_reset_trigger(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

665

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

67

if (optc->dlg_otg_param.vstartup_start == 0) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

676

void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

678

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

711

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

715

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

73

VSTARTUP_START, optc->dlg_otg_param.vstartup_start);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

755

void optc1_wait_for_state(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

758

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

76

VUPDATE_OFFSET, optc->dlg_otg_param.vupdate_offset,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

77

VUPDATE_WIDTH, optc->dlg_otg_param.vupdate_width);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

779

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

789

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

792

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

80

VREADY_OFFSET, optc->dlg_otg_param.vready_offset);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

818

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

821

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

83

static void optc1_disable_stereo(struct timing_generator *optc)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

85

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

855

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

862

struct optc *optc1 = DCN10TG_FROM_TG(optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

96

static uint32_t get_start_vline(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

32

container_of(tg, struct optc, base)

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

443

void dcn10_timing_generator_init(struct optc *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

466

void optc1_read_otg_state(struct optc *optc1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

470

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

474

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

478

void optc1_program_vline_interrupt(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

483

struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

485

bool optc1_disable_crtc(struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

487

bool optc1_is_counter_moving(struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

489

void optc1_get_position(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

492

uint32_t optc1_get_vblank_counter(struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

495

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

502

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

505

void optc1_wait_for_state(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

508

void optc1_set_blank(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

511

bool optc1_is_blanked(struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

514

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

518

struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

520

void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

522

void optc1_disable_reset_trigger(struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

524

void optc1_lock(struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

526

void optc1_unlock(struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

528

void optc1_enable_optc_clock(struct timing_generator *optc, bool enable);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

531

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

535

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

538

void optc1_program_stereo(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

541

bool optc1_is_stereo_left_eye(struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

543

void optc1_clear_optc_underflow(struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

545

void optc1_tg_init(struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

547

bool optc1_is_tg_enabled(struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

549

bool optc1_is_optc_underflow_occurred(struct timing_generator *optc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

551

void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

553

bool optc1_get_otg_active_size(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

558

struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

562

bool optc1_configure_crc(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

565

bool optc1_get_crc(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

703

struct optc *tgn10 =

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

704

kzalloc(sizeof(struct optc), GFP_KERNEL);

sys/dev/drm/amd/display/dc/inc/hw/timing_generator.h

143

void (*program_vline_interrupt)(struct timing_generator *optc,

sys/dev/drm/amd/display/dc/inc/hw/timing_generator.h

159

bool (*get_otg_active_size)(struct timing_generator *optc,

usr.bin/crunch/crunchgen/crunchgen.c

132

int optc;

usr.bin/crunch/crunchgen/crunchgen.c

148

while ((optc = getopt(argc, argv, "lh:m:c:e:p:foq")) != -1) {

usr.bin/crunch/crunchgen/crunchgen.c

149

switch (optc) {

usr.sbin/ppp/main.c

212

int optc, newmode, arg;

usr.sbin/ppp/main.c

215

optc = 0;

usr.sbin/ppp/main.c

220

for (arg = 1; arg < argc && *argv[arg] == '-'; arg++, optc++) {

usr.sbin/ppp/main.c

231

optc--; /* this option isn't exclusive */

usr.sbin/ppp/main.c

241

optc--; /* this option isn't exclusive */

usr.sbin/ppp/main.c

243

optc--; /* this option isn't exclusive */

usr.sbin/ppp/main.c

245

optc--; /* nor is the argument */

usr.sbin/ppp/main.c

255

optc--; /* this option isn't exclusive */

usr.sbin/ppp/main.c

271

if (optc > 1) {