AGG_WR
AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
AGG_WR(ess, PORT_HOSTINT_STAT, status, 1);
AGG_WR(ess, PORT_INT_STAT, 1, 2);
AGG_WR(ess, PORT_HWVOL_MASTER, HWVOL_NOP, 1);
AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_READ | regno, 1);
AGG_WR(ess, PORT_CODEC_REG, data, 2);
AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_WRITE | regno, 1);
AGG_WR(ess, PORT_RINGBUS_CTRL, data, 4);
AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
AGG_WR(ess, PORT_DSP_DATA, data, 2);
AGG_WR(ess, PORT_DSP_DATA, data, 2);
AGG_WR(ess, PORT_INT_STAT, 1, 2);
AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_INT_ENABLED
AGG_WR(ess, PORT_HOSTINT_CTRL, ~HOSTINT_CTRL_DSOUND_INT_ENABLED
AGG_WR(ess, PORT_INT_STAT, 1, 2);
AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
AGG_WR(ess, PORT_WAVCACHE_DATA, data, 2);
AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_AC97_SWRESET, 4);
AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
AGG_WR(ess, PORT_GPIO_MASK, 0xff6, 2);
AGG_WR(ess, PORT_GPIO_DIR, data | 0x009, 2);
AGG_WR(ess, PORT_GPIO_DATA, 0x000, 2);
AGG_WR(ess, PORT_GPIO_DATA, 0x001, 2);
AGG_WR(ess, PORT_GPIO_DATA, 0x009, 2);
AGG_WR(ess, PORT_GPIO_DIR, data, 2);
AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_SOFT_RESET, 2);
AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_RESET, 2);
AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
AGG_WR(ess, PORT_HOSTINT_CTRL,HOSTINT_CTRL_HWVOL_ENABLED, 2);
AGG_WR(ess, PORT_WAVCACHE_CTRL,
AGG_WR(ess, PORT_RINGBUS_CTRL,
AGG_WR(ess, PORT_RINGBUS_CTRL_B, RINGBUS_CTRL_SPDIF |
AGG_WR(ess, PORT_ASSP_CTRL_B, 0x00, 1);
AGG_WR(ess, PORT_ASSP_CTRL_A, 0x03, 1);
AGG_WR(ess, PORT_ASSP_CTRL_C, 0x00, 1);
AGG_WR(ess, PORT_GPIO_MASK, 0x9ff, 2);
AGG_WR(ess, PORT_GPIO_DIR,
AGG_WR(ess, PORT_GPIO_DATA, 0x200, 2);
AGG_WR(ess, PORT_RINGBUS_CTRL,
AGG_WR(ess, PORT_RINGBUS_CTRL,
AGG_WR(ess, PORT_RINGBUS_CTRL,
AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
AGG_WR(ess, PORT_HOSTINT_STAT, 0xff, 1);