Symbol: mpc
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1055
dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1948
struct mpc *mpc = dc->res_pool->mpc;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2000
mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2005
new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2008
mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2011
mpc->funcs->assert_mpcc_idle_before_connect(
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2012
dc->res_pool->mpc, mpcc_id);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2015
new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2586
res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
297
pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
884
struct mpc *mpc = dc->res_pool->mpc;
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
890
mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
896
mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
396
pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
106
struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
108
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
111
return &(mpc->mpcc_array[mpcc_id]);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
126
bool mpc1_is_mpcc_idle(struct mpc *mpc, int mpcc_id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
128
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
142
void mpc1_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
144
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
177
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
185
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
203
new_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
240
mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
245
mpc1_update_stereo_mix(mpc, sm_cfg, mpcc_id);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
265
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
269
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
346
void mpc1_mpc_init(struct mpc *mpc)
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
348
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
358
mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
368
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
371
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
392
mpcc = mpc1_get_mpcc(mpc, mpcc_id);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
40
void mpc1_set_bg_color(struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
403
struct mpcc *mpcc_bottom = mpc1_get_mpcc(mpc, bot_mpcc_id);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
414
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
418
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
44
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
63
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
67
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
68
struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
77
mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
82
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
86
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
96
void mpc1_assert_idle_mpcc(struct mpc *mpc, int id)
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c
98
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h
119
struct mpc base;
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h
136
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h
145
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h
150
struct mpc *mpc);
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h
153
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h
157
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h
162
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h
167
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h
171
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h
175
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h
179
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.h
187
struct mpc *mpc,
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
1449
pool->base.mpc = dcn10_mpc_create(ctx);
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
1450
if (pool->base.mpc == NULL) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
666
static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
883
if (pool->base.mpc != NULL) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
884
kfree(TO_DCN10_MPC(pool->base.mpc));
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
885
pool->base.mpc = NULL;
sys/dev/drm/amd/display/dc/inc/core_types.h
146
struct mpc *mpc;
sys/dev/drm/amd/display/dc/inc/hw/mpc.h
122
struct mpc *mpc,
sys/dev/drm/amd/display/dc/inc/hw/mpc.h
143
struct mpc *mpc,
sys/dev/drm/amd/display/dc/inc/hw/mpc.h
162
struct mpc *mpc,
sys/dev/drm/amd/display/dc/inc/hw/mpc.h
174
void (*mpc_init)(struct mpc *mpc);
sys/dev/drm/amd/display/dc/inc/hw/mpc.h
187
struct mpc *mpc,
sys/dev/drm/amd/display/dc/inc/hw/mpc.h
195
void (*wait_for_idle)(struct mpc *mpc, int id);
sys/dev/drm/amd/display/dc/inc/hw/mpc.h
197
void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id);
sys/dev/drm/amd/display/dc/inc/hw/mpc.h
200
struct mpc *mpc,
sys/dev/netif/em/if_em.c
4102
adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
sys/dev/netif/em/if_em.c
4175
adapter->stats.mpc + adapter->stats.cexterr);
sys/dev/netif/em/if_em.c
4246
(long long)adapter->stats.mpc);
sys/dev/netif/emx/if_emx.c
3646
sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
sys/dev/netif/emx/if_emx.c
3709
sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr);
sys/dev/netif/emx/if_emx.c
3775
(long long)sc->stats.mpc);
sys/dev/netif/ig_hal/e1000_hw.h
557
u64 mpc;
sys/dev/netif/igb/if_igb.c
3184
stats->mpc += E1000_READ_REG(hw, E1000_MPC);
sys/dev/netif/igb/if_igb.c
3290
stats->ruc + stats->roc + stats->mpc + stats->cexterr);
sys/dev/netif/ix/if_ix.c
3546
stats->mpc[0] += IXGBE_READ_REG(hw, IXGBE_MPC(0));
sys/dev/netif/ix/ixgbe_type.h
3805
u64 mpc[8];