sys/dev/drm/amd/amdgpu/vce_v2_0.c

174

WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

323

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

325

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

339

tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

341

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

371

orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

374

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

377

WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

198

data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

200

WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

222

data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

224

WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

536

WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

608

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), 0x3F, ~0x3F);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

835

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

837

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

859

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

861

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);