sys/dev/drm/amd/amdgpu/vce_v3_0.c

193

data = RREG32(mmVCE_UENC_CLOCK_GATING_2);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

196

WREG32(mmVCE_UENC_CLOCK_GATING_2, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

218

data = RREG32(mmVCE_UENC_CLOCK_GATING_2);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

220

WREG32(mmVCE_UENC_CLOCK_GATING_2, data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

830

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

833

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

855

data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

857

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data);