sys/dev/drm/amd/amdgpu/vce_v2_0.c

122

uint32_t status = RREG32(mmVCE_STATUS);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

236

WREG32_P(mmVCE_STATUS, 1, ~1);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

265

WREG32_P(mmVCE_STATUS, 0, ~1);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

305

WREG32(mmVCE_STATUS, 0);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

242

uint32_t status = RREG32(mmVCE_STATUS);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

352

WREG32(mmVCE_STATUS, 0);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

630

if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {

sys/dev/drm/amd/amdgpu/vce_v3_0.c

635

if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {

sys/dev/drm/amd/amdgpu/vce_v4_0.c

131

RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

299

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

306

MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

311

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

360

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), VCE_STATUS__JOB_BUSY_MASK,

sys/dev/drm/amd/amdgpu/vce_v4_0.c

372

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

393

WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

715

if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {

sys/dev/drm/amd/amdgpu/vce_v4_0.c

720

if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {