mmUVD_VCPU_CACHE_SIZE2
WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,