sys/dev/drm/amd/amdgpu/uvd_v4_2.c

558

WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

268

WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

600

WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

677

WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

685

WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

826

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

293

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

301

WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

362

WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

371

WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,