sys/dev/drm/amd/amdgpu/uvd_v5_0.c

662

data2 = RREG32(mmUVD_SUVD_CGC_CTRL);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

701

WREG32(mmUVD_SUVD_CGC_CTRL, data2);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1316

data2 = RREG32(mmUVD_SUVD_CGC_CTRL);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1356

WREG32(mmUVD_SUVD_CGC_CTRL, data2);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1593

data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1640

WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

534

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

545

WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

607

data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

618

WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

672

WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);