sys/dev/drm/amd/amdgpu/uvd_v4_2.c

218

if (RREG32(mmUVD_STATUS) != 0)

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

268

WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

322

status = RREG32(mmUVD_STATUS);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

348

WREG32_P(mmUVD_STATUS, 0, ~(1<<2));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

393

status = RREG32(mmUVD_STATUS);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

436

WREG32(mmUVD_STATUS, 0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

215

if (RREG32(mmUVD_STATUS) != 0)

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

366

status = RREG32(mmUVD_STATUS);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

392

WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

454

WREG32(mmUVD_STATUS, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1149

(RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

548

if (RREG32(mmUVD_STATUS) != 0)

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

789

status = RREG32(mmUVD_STATUS);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

816

WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

893

WREG32(mmUVD_STATUS, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1032

status = RREG32_SOC15(UVD, k, mmUVD_STATUS);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1062

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1468

(RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

809

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

895

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

917

MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1131

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1161

WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1210

return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1218

SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

225

if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

782

tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

783

WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

854

status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

888

tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

889

WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);