sys/dev/drm/amd/amdgpu/uvd_v4_2.c

311

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

313

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

315

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

332

WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

335

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

432

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

319

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

350

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

360

WREG32(mmUVD_SOFT_RESET, 0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

376

WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

379

WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

445

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

732

WREG32(mmUVD_SOFT_RESET,

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

772

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

782

WREG32(mmUVD_SOFT_RESET, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

884

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1012

WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1025

WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1042

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1046

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1139

WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

862

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

882

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

911

MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

976

WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1032

WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1140

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1153

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1157

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

838

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

845

tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

848

WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

864

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

868

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,