sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

264

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

324

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

364

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

76

return RREG32(mmUVD_RBC_RB_WPTR);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

90

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

421

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

73

return RREG32(mmUVD_RBC_RB_WPTR);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

87

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

111

return RREG32(mmUVD_RBC_RB_WPTR);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

142

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

844

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

106

return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1092

WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

140

WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1092

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1178

int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1267

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1285

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

919

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,