sys/dev/drm/amd/amdgpu/uvd_v4_2.c

361

WREG32(mmUVD_RBC_RB_RPTR, 0x0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

363

ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

62

return RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

418

WREG32(mmUVD_RBC_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

420

ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

59

return RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

81

return RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

841

WREG32(mmUVD_RBC_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

843

ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1089

WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1091

ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

75

return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1087

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1091

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1180

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1253

return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

914

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

918

ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);