sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

236

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

266

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

291

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

297

reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

299

WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

326

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

303

WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1462

WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

716

WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1740

WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

947

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1173

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1182

SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1188

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

713

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

718

WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

728

data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

731

WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

971

tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

974

WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);