Symbol: mmUVD_MPC_SET_MUXA0
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
296
WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
342
WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
764
WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1004
WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
1009
WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0,
sys/dev/drm/amd/amdgpu/vcn_v1_0.c
811
WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,