sys/dev/drm/amd/amdgpu/uvd_v4_2.c

309

WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

414

WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

315

WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

357

WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

441

WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

452

WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

880

WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

891

WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1021

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1133

WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1147

WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

857

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

914

MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

970

WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1035

WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

842

WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,